XMC-6280
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 14 - http://www.acromag.com
- 14 -
www.acromag.com
PCIE INTERFACE LOGIC
SFP+ Module Connectors
DDR3
Clock Generation
The XMC-6280 host interface is through PCI Express 2.0 which provides a
5Gbps interface to the carrier/CPU board. The PCIe interface supports 8
physical functions (PF). SR-IOV is supported on 4 PF with 128 virtual
functions (VF). It supports x1, x2, x4 and x8 link widths. Maximum payload
sizes and memory read request sizes of 128B to 2KB are supported, with up
to 128 outstanding PCIe reads.
The PCIe Device and Vendor IDs are as follows:
Device ID
0x4484
Vendor ID
0x1425
Subsystem ID
0x0000
Subsystem Vendor ID
0x16D5
The board contains four small form-factor pluggable plus (SFP+) connectors
and cage assemblies that accept SFP+ modules as well as SFP modules. The
SFP+ interfaces are wired directly to the T4 ASICs integrated full-duplex
Ethernet MACs. The appropriate SFP rate will be configured automatically by
the T4 firmware. Firmware will also be in control of the other SFP signals
including Tx_Fault, Tx_Disable, Rx_LOS and Mod_ABS.
There is a 64 Meg x 72-bit of DDR3 memory onboard for the purpose of
storing connection states and buffers for up to 32K offloaded connections.
Five DDR3 memory devices are used to form a 72-bit data bus. Each of the
devices are 64 Meg x 16 bit (1Gb) in size.
There is one onboard 50MHz XTAL providing the core clock to the T4 ASIC.
This XTAL is all that is needed in order for the ASIC to internally produce the
necessary clocks needed for operation.
