VPX4810 PCIe PMC/XMC 3U Carrier
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 13 -
http://www.acromag.com
- 13 -
www.acromag.com
VPX Backplane Connector Pinouts
VPX P0 Connector-Power and System Controls
Table 2.2 indicates the pin assignments for the VPX 3U assignments at the P0 connector. The connector
consists of 8 wafers with up to 7 signals on each. The system management bus signals SM0, SM1, SM2, and
SM3 use I
2
C to implement the Intelligent Platform Management Bus (IPMB) per VITA 46.11.
The VPX4810 CAN
NOT BE PLUGGED INTO A 6U VPX SYSTEM DUE TO POWER INCOMPATIBILITIES BETWTEEN THE 3U AND 6U
FORM FACTORS. PLUGGING THE VPX4810 INTO A 6U SYSTEM WILL DAMAGE THE BOARD!
Refer to the VPX specifications for additional information on these signals.
Wafer
Row G
Row F
Row E
Row D
Row C
Row B
Row A
1
+12V
+12V
+12V
NC
+3.3V
+3.3V
+3.3V
2
+12V
+12V
+12V
NC
+3.3V
+3.3V
+3.3V
3
+5V
+5V
+5V
NC
+5V
+5V
+5V
4
SM2
SM3
GND
12V_AUX
GND
SYSRST
NVMRO
5
GAP
GA4
GND
3.3V_AUX
GND
SM0
SM1
6
GA3
GA2
GND
+12V_AU
GND
GA1
GA0
7
TCK
GND
TDO
TDI
GND
TMS
TRST
8
GND
REF_CLK-
GND
RES
RES
GND
Note:
BOLD ITALIC
signals are NOT USED by this carrier board.
VPX P1 Connector
–
PCIe
The VPX 3U P1 connector contains the high speed PCIe signals. The VPX4810 is compliant to VITA 46.4 with up
to 8 lanes and PCIe.
Wafer
Row G
Row F
Row E
Row D
Row C
Row B
Row A
1
RES
GND
L0-TX-
L0-TX+
GND
L0-RX-
L0-RX+
2
GND
L1-TX-
L1-TX+
GND
L1-RX-
L1-RX+
GND
3
VBAT
GND
L2-TX-
L2-TX+
GND
L2-RX-
L2-RX+
4
GND
L3-TX-
L3-TX+
GND
L3-RX-
L3-RX+
GND
5
SYS_CON
GND
L4-TX-
L4-TX+
GND
L4-RX-
L4-RX+
6
GND
L5-TX-
L5-TX+
GND
L5-RX-
L5-RX+
GND
7
REG_CLK_SE
GND
L6-TX-
L6-TX+
GND
L6-RX-
L6-RX+
8
GND
L7-TX-
L7-TX+
GND
L7-RX-
L7-RX+
GND
9
P1-SE4
GND
L8-TX-
L8-TX+
GND
L8-RX-
L8-RX+
10
GND
L9-TX-
L9-TX+
GND
L9-RX-
L9-RX+
GND
11
P1-SE5
GND
L10-TX-
L10-TX+
GND
L10-RX-
L10-RX+
Note:
BOLD ITALIC
signals are NOT USED by this carrier board.
