Acromag IP521-64 Series User Manual Download Page 6

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SERIES IP521 INDUSTRIAL I/O PACK EIA/TIA-422B SERIAL COMMUNICATION MODULE
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3.0 PROGRAMMING INFORMATION

ADDRESS MAPS

This board is addressable in the Industrial Pack I/O space to

control the interface configuration, data transfer, and steering logic
of eight EIA/TIA-422B serial ports. As such, three types of
information are stored in the I/O space: control, status, and data.
These registers are listed below along with their mnemonics used
throughout this manual.

The I/O space may be as large as 64, 16-bit words (128 bytes)

using address lines A1..A6, but the IP521 uses 64 lower byte
locations of this space. The I/O space address map for the IP521 is
shown in Table 3.1. Note that the base address for the IP module
I/O space (see your carrier board instructions) must be added to the
addresses shown to properly access the I/O space. All accesses
are performed on an 8-bit word basis (D0..D7).

This manual is presented using the “Big Endian” byte ordering

format. Big Endian is the convention used in the Motorola 68000
microprocessor family and is the VMEbus convention. In Big
Endian, the lower-order byte is stored at odd-byte addresses. Thus,
byte accesses are done on odd address locations. The Intel x86
family of microprocessors use the opposite convention, or “Little
Endian” byte ordering. Little Endian uses even-byte addresses to
store the low-order byte. As such, use of this module on a PC
carrier board will require the use of the even address locations to
access the 8-bit data, while a VMEbus carrier requires the use of
odd address locations.

SERIAL DATA REGISTERS (Per Serial Port):

RBR

Receiver Buffer Register

THR

Transmitter Holding Register

SERIAL STATUS REGISTERS (Per Serial Port):

LSR

Line Status Register

MSR

Modem Status Register

ISR

Interrupt Status Register

SERIAL CONTROL REGISTERS (Per Serial Port):

LCR

Line Control Register

FCR

FIFO Control Register

MCR

Modem Control Register

DLL

Divisor Latch LSB

DLM

Divisor Latch MSB

IER

Interrupt Enable Register

SCR

Scratch Pad/Interrupt Vector Register

EFR

Enhanced Feature Register

XON-1

XON-1 Low Byte

XON-2

XON-2 High Byte

XOFF-1

XOFF-1 Low Byte

XOFF-2

XOFF-2 High Byte

Shaded registers are accessible only after writing “BF” to the line
Control Register (LCR).

Note that some functions share the same register address. For

these items, the address lines are used along with the LCR (Line
Control Register) and/or the read and write signals to determine the
function required. The DLL and DLM registers are only accessible
when LCR bit-7 is set to “1”. The EFR, Xon 1,2, and Xoff 1,2
locations are accessible only when the LCR is set to “BF” hex.

The IP521 is an eight port RS422 module. Memory map Table

3.1 lists the addresses and registers corresponding to Port A.
Detailed register maps for Ports B to H are not given. Since all
registers corresponding to all Ports are listed in the same order, it is
possible to determine the address for Ports B to H by using Port A
and adding the offset given in the table below. For example, Port E’s
LCR can be accessed at word address 40 + 06 or 46 hex which is
Port A LCR at 06 hex plus Port E Offset at 40 hex.

PORT

ADDRESS SPACE OFFSET