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SERIES IP1K100 INDUSTRIAL I/O PACK                                        RECONFIGURABLE DIGITAL I/O MODULE
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Table 2.1:  IP1K100 Field I/O Pin Connections (P2)

Pin Description

Pin Description

RS485

TTL

Pin

Number

RS485

TTL

Pin

Number

I/O00+

I/O00

1

I/O12-

I/O25

26

I/O00-

I/O01

2

I/O13+

I/O26

27

I/O01+

I/O02

3

I/O13-

I/O27

28

I/O01-

I/O03

4

I/O14+

I/O28

29

I/O02+

I/O04

5

I/O14-

I/O29

30

I/O02-

I/O05

6

I/O15+

I/O30

31

I/O03+

I/O06

7

I/O15-

I/O31

32

I/O03-

I/O07

8

I/O16+

I/O32

33

I/O04+

I/O08

9

I/O16-

I/O33

34

I/O04-

I/O09

10

I/O17+

I/O34

35

I/O05+

I/O10

11

I/O17-

I/O35

36

I/O05-

I/O11

12

I/O18+

I/O36

37

I/O06+

I/O12

13

I/O18-

I/O37

38

I/O06-

I/O13

14

I/O19+

I/O38

39

I/O07+

I/O14

15

I/O19-

I/O39

40

I/O07-

I/O15

16

I/O20+

I/O40

41

I/O08+

I/O16

17

I/O20-

I/O41

42

I/O08-

I/O17

18

I/O21+

I/O42

43

I/O09+

I/O18

19

I/O21-

I/O43

44

I/O09-

I/O19

20

I/O22+

I/O44

45

I/O10+

I/O20

21

I/O22-

I/O45

46

I/O10-

I/O21

22

I/O23+

I/O46

47

I/O11+

I/O22

23

I/O23-

I/O47

48

I/O11-

I/O23

24

NC

NC

49

I/O12+

I/O24

25

GND

GND

50

Table 2.2:  IP1K100 Model Channel Assignments

Model

I/O Register Bits

See Table 2.1 for Pin Assignments

IP1K100-0024

Differential/RS485  Channels 

±

0 to 

±

23

IP1K100-2412

Differential /RS485
Channels 

±

12 to 

±

23

TTL Channels

0 to 23

IP1K100-4800

TTL Channels 0 to 47

I/O Noise and Grounding Considerations

The IP1K100 is non-isolated between the logic and field I/O

grounds since output common is electrically connected to the IP
module ground.  Consequently, the field I/O connections are not
isolated from the carrier board and backplane.  Two ounce copper
ground plane foil has been employed in the design of this model to
help minimize the effects of ground bounce, impedance drops, and
switching transients.  However, care should be taken in designing
installations without isolation to avoid noise pickup and ground loops
caused by multiple ground connections.

To minimize high levels of EMI the signal ground connection at

the field I/O port (pin 50) should be used to provide a path for
induced common-mode noise and currents.  The ground path
provides a low-impedance path to reduce emissions.

EIA RS485/RS422 communication distances are generally

limited to less than 4000 feet.  To minimize transmission-line
problems, all nodes connected to the cable must use minimum stub
length connections.  The optimal configuration for the RS485/RS422
bus is a daisy-chain connection from node 1 to node 2 to node 3 to

node n.  The bus must form a single continuous path, and the nodes
in the middle of the bus must not be at the ends of long branches,
spokes, or stubs.  See Drawing 4501-702 for example connection
and termination practices.

Transmission line signal reflections can be minimized with

proper termination.  The EIA RS485/RS422 standard allows up to
32 driver/receivers to be connected to a single bus.  Termination
resistors should only be used at the two extreme ends of the bus
and not at each of the nodes of the bus.  Terminiation resistors are
not provided on the IP1K100.  They can be added to the field wiring
as near to the IP module as possible.

IP Logic Interface Connector (P1)

P1 of the IP module provides the logic interface to the mating

connector on the carrier board.  This connector is a 50-pin female
receptacle header (AMP 173279-3 or equivalent) which mates to the
male connector of the carrier board (AMP 173280-3 or equivalent).
This provides excellent connection integrity and utilizes gold-plating
in the mating area.  Threaded metric M2 screws and spacers are
supplied with the IP module to provide additional stability for harsh
environments (see Drawing 4501-434 for assembly details).  Field
and logic side connectors are keyed to avoid incorrect assembly.
The pin assignments of P1 are standard for all IP modules
according to the Industrial I/O Pack Specification (see Table 2.3).
Note that the IP1K100 does not utilize all of the logic signals defined
for the P1 connector and these are indicated in BOLD ITALICS.

Table 2.3:  Standard Logic Interface Connections (P1)

Pin Description

Number

Pin Description

Number

GND

1

GND

26

CLK

2

+5V

27

Reset

3

R/W

28

D00

4

IDSEL

29

D01

5

DMAReq0

30

D02

6

MEMSEL

31

D03

7

DMAReq1

32

D04

8

IntSel

33

D05

9

DMAck0

34

D06

10

IOSEL

35

D07

11

RESERVED

36

D08

12

A1

37

D09

13

DMAEnd

38

D10

14

A2

39

D11

15

ERROR

40

D12

16

A3

41

D13

17

INTReq0

42

D14

18

A4

43

D15

19

INTReq1

44

BS0

20

A5

45

BS1

21

STROBE

46

-12V

22

A6

47

+12V

23

ACK

48

+5V

24

RESERVED

49

GND

25

GND

50

 Asterisk (*) is used to indicate an active-low signal.
 BOLD ITALIC Logic Lines are NOT USED by this IP Model.

Summary of Contents for IP1K100 Series

Page 1: ...ard USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 2001 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 681 B02H012 retired ...

Page 2: ...PAIR ASSISTANCE 16 PRELIMINARY SERVICE PROCEDURE 16 6 0 SPECIFICATIONS 16 PHYSICAL 16 ENVIRONMENTAL 16 EIA RS485 RS422 TRANSCEIVERS 17 TTL TRANSCEIVERS 17 INDUSTRIAL I O PACK COMPLIANCE 17 APPENDIX 18 CABLE MODEL 5025 551 18 CABLE MODEL 5025 552 18 TRANSITION MODULE MODEL TRANS GP 18 DRAWINGS Page 4501 908 IP1K100 BLOCK DIAGRAM 19 4501 702 RS485 I O CONNECTIONS 20 4501 434 IP MECHANICAL ASSEMBLY 2...

Page 3: ...as its own 8 bit ID information which is accessed via data transfers in the ID Read space 16 bit 8 bit I O Channel register Read Write is performed through D16 or D08 EO data transfer cycles in the IP module I O space High Speed Access times for all data transfer cycles are described in terms of wait states For the supplied IP module example wait states are utilized for all read and write operatio...

Page 4: ...for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power The board utilizes static sensitive components and should only be handled at a static safe workstation CA...

Page 5: ...y limited to less than 4000 feet To minimize transmission line problems all nodes connected to the cable must use minimum stub length connections The optimal configuration for the RS485 RS422 bus is a daisy chain connection from node 1 to node 2 to node 3 to node n The bus must form a single continuous path and the nodes in the middle of the bus must not be at the ends of long branches spokes or s...

Page 6: ...nd configuration is implemented with no special hardware or cables An example program written in C is available from Acromag ActiveX Control or VxWorks software implements configuration of the IP1K100 over the IP bus The program requires your configuration file to be in the Intel Hex format Using the Altera MAX PLUS II software you can generate the required hex file as follows 1 In the MAX PLUS II...

Page 7: ...rmation required for the module The IP1K100 ID space does not contain any variable e g unique calibration information ID space bytes are addressed using only the odd addresses in a 64 byte block on the Big Endian VMEbus Even addresses are used on the Little Endian PC ISA or PCI buses The IP1K100 ID space will read differently in configuration mode than it does in user mode In configuration mode th...

Page 8: ...ormat Big Endian is the convention used in the Motorola 68000 and PowerPC microprocessor family and is the VMEbus convention In Big Endian the lower order byte is stored at odd byte addresses The Intel x86 family of microprocessors uses the opposite convention or Little Endian byte ordering Little Endian uses even byte addresses to store the low order byte As such use of the memory map for this mo...

Page 9: ...f 8 channels Setting a bit high configures the data direction for the identified channels as output Setting the control bit low configures the corresponding channel s data direction for input The default power up state of these registers is logic low Thus all channels are configured as inputs on system reset or power up The unused upper nibble D15 to D12 of the register at base address 08H will al...

Page 10: ...ata Bit 01 Data Bit 00 Ch07 Ch06 Ch05 Ch04 Ch03 Ch02 Ch01 Ch00 The unused upper 8 bits of this register are Not Used and will always read low 0 s for D16 accesses All bits are set to 0 following a reset which means that all interrupts are cleared Interrupt Polarity Registers Read Write Base 11H The Interrupt Polarity Register determines the level that will cause a channel interrupt to occur for ea...

Page 11: ...h and Low registers This Length value is used by the hardware to set the number of clock cycles the Shift High and Shift Low values are shifted to the Clock Generator chip See the program procedure example which follows for information on determining the value to write to this register A write access to this register requires one wait state A software or hardware reset will clear the contents of t...

Page 12: ...interrupts input channel bandwidth should be limited to reduce the possibility of missing channel interrupts For a given input channel this could happen if multiple changes occur before the channel s interrupt is serviced The response time of the input channels should also be considered when calculating this bandwidth The total response time is the sum of the input buffer response time plus the in...

Page 13: ...own in Drawing 4501 908 as you review this material FIELD INPUT OUTPUT SIGNALS The field I O interface to the IP module is provided through connector P2 refer to Table 2 1 These pins are tied to the inputs and outputs of EIA RS485 RS422 line transceivers or TTL transceivers RS485 signals received are converted from the required EIA RS485 RS422 voltages signals to the TTL levels required by the FPG...

Page 14: ...he address signals RAMa1 to RAMa16 data signals RAMd0 to RAMd15 and the read write control signals nWE_RAM nBLE_RAM nBHE_RAM and nOE_RAM as listed in Table 4 1 The RAM device is the Integrated Device Technology IDT71016 or the Cypress Cy7C1021 IP Bus Interface The IP1K100 interfaces to the carrier board per IP Module specification ANSI VITA 4 1995 The FPGA signals utilized are 16 data lines DATA0 ...

Page 15: ... 76 GND GND 77 VCC_CKLK 2 5Volts 78 nBS0 Input IP Bus 79 IP CLK GCLK1 IP Module Clock 80 nBS1 Input IP Bus 81 GND_CKLK GND Pin Signal I O 82 GND GND 83 DIO12 Bi Dir 84 VCCIO 3 3Volts 85 DIO13 Bi Dir 86 DIO14 Bi Dir 87 DIO15 Bi Dir 88 DIO16 Bi Dir 89 DIO17 Bi Dir 90 DIO18 Bi Dir 91 VCCINT 2 5Volts 92 DIO19 Bi Dir 93 DIO20 Bi Dir 94 DIO21 Bi Dir 95 DIO22 Bi Dir 96 DIO23 Bi Dir 97 DIO24 Bi Dir 98 VCC...

Page 16: ... REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and whe...

Page 17: ...rrent 250mA Maximum Input Hysteresis 70mV VCM 0V TTL TRANSCEIVERS Channel Configuration Up to 48 non isolated TTL signals Selected in blocks of 8 channels when ordered Integrated Circuit Device Pericom PI74FCT623T http www pericom com INDUSTRIAL I O PACK COMPLIANCE Specification This device meets or exceeds all written Industrial I O Pack specifications per ANSI VITA 4 1995 for 8MHz or 32MHz opera...

Page 18: ... Pack modules Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 50 correspond to P2 pins 1 50 on the Industrial I O Pack IP Each Industrial I O Pack IP has its own unique P2 pin assignments Refer to the IP module manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 464 Field Wirin...

Page 19: ...SERIES IP1K100 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL I O MODULE ___________________________________________________________________________________________ 19 ...

Page 20: ...SERIES IP1K100 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL I O MODULE ___________________________________________________________________________________________ 20 ...

Page 21: ...SERIES IP1K100 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL I O MODULE ___________________________________________________________________________________________ 21 ...

Page 22: ...SERIES IP1K100 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL I O MODULE ___________________________________________________________________________________________ 22 ...

Page 23: ...SERIES IP1K100 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL I O MODULE ___________________________________________________________________________________________ 23 ...

Page 24: ...SERIES IP1K100 INDUSTRIAL I O PACK RECONFIGURABLE DIGITAL I O MODULE ___________________________________________________________________________________________ 24 4 5 0 1 4 6 4 A ...

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