SERIES IP1K100 INDUSTRIAL I/O PACK RECONFIGURABLE DIGITAL I/O MODULE
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The information contained in this manual is subject to change
without notice. Acromag, Inc. makes no warranty of any kind with
regard to this material, including, but not limited to, the implied
warranties of merchantability and fitness for a particular purpose.
Further, Acromag, Inc. assumes no responsibility for any errors that
may appear in this manual and makes no commitment to update, or
keep current, the information contained in this manual. No part of
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prior written consent of Acromag, Inc.
Table of Contents
Page
1.0 GENERAL INFORMATION…...........................................
2
KEY IP1K100 FEATURES................................................
3
INDUSTRIAL I/O PACK INTERFACE FEATURES.….....
3
SIGNAL INTERFACE PRODUCTS..........................…....
3
IP MODULE ActiveX CONTROL SOFTWARE…….........
3
IP MODULE VxWORKS SOFTWARE……………………
4
2.0 PREPARATION FOR USE..................................….........
4
UNPACKING AND INSPECTION..................…..............
4
CARD CAGE CONSIDERATIONS.............….................
4
BOARD CONFIGURATION..................….......................
4
CONNECTORS...............................….............................
4
IP Field I/O Connector (P2)...............…........................
4
I/O Noise and Grounding Considerations......…...........
5
IP Logic Interface Connector (P1)..............…...............
5
3.0 PROGRAMMING INFORMATION...........…....................
5
IN-SYSTEM CONFIGURATION ADDRESS MAPS.........
5
IP1K100 Configuration Procedure...…………….……....
6
Altera FPGA Logic Requirements…...…………….…....
6
IP Identification Space..........….....................................
7
Example Altera FPGA Design........................................
7
Control Register............................…….………..……....
8
Input/Output Registers...........……………........…..........
9
Direction Control Register…..............................….........
9
Interrupt Enable Register…………………….…..………
9
Interrupt Type Configuration Register.......…...…...........
9
Interrupt Status Register.....................…............…........
10
Interrupt Polarity Register...................…........…............
10
Interrupt Vector Register..............….....…....…..............
10
Memory Data Register……………………………………
10
Memory Address Register………………….……………
11
Clock Generator Shift High Register…………………….
11
Clock Generator Shift Low Register……………….…….
11
Clock Generator Length Register………………………..
11
Clock Generator Trigger Register…………………...…..
11
Program Procedure to Set Clock Generator Frequency
11
IP1K100 PROGRAMMING CONSIDERATIONS.............
11
Programming Interrupts.......….............................…....
12
4.0 THEORY OF OPERATION..............…............................
13
FIELD INPUT/OUTPUT SIGNALS...…............................
13
LOGIC/POWER INTERFACE........................……..........
13
EIA-RS485 AND RS422 SERIAL INTERFACE…….…..
13
SIGNAL PIN ASSIGNMENTS……………………………..
14
5.0 SERVICE AND REPAIR.....................................….........
16
SERVICE AND REPAIR ASSISTANCE.........….............
16
PRELIMINARY SERVICE PROCEDURE......................
16
6.0 SPECIFICATIONS.....................................…...................
16
PHYSICAL……………………........................................
16
ENVIRONMENTAL................................…......................
16
EIA-RS485/RS422 TRANSCEIVERS...….......................
17
TTL TRANSCEIVERS………………………………………
17
INDUSTRIAL I/O PACK COMPLIANCE......….................
17
APPENDIX....................................................…...............
18
CABLE: MODEL 5025-551...........................…...…...........
18
CABLE: MODEL 5025-552................................…............
18
TRANSITION MODULE: MODEL TRANS-GP.…............
18
DRAWINGS
Page
4501-908 IP1K100 BLOCK DIAGRAM.......................…..
19
4501-702 RS485 I/O CONNECTIONS…………………...
20
4501-434 IP MECHANICAL ASSEMBLY................…..…
21
4501-462 CABLE 5025-550 (NON-SHIELDED).......…....
22
4501-463 CABLE 5025-551 (SHIELDED)...................….
23
4501-464 TERMINATION PANEL 5025-552..............….
24
4501-465 TRANSITION MODULE TRANS-GP..........….
24
IMPORTANT SAFETY CONSIDERATIONS
It is very important for the user to consider the possible adverse
effects of power, wiring, component, sensor, or software failures
in designing any type of control or monitoring system. This is
especially important where economic property loss or human life is
involved. It is important that the user employ satisfactory
overall system design. It is agreed between the Buyer and
Acromag, that this is the Buyer's responsibility.
All trademarks are the property of their respective owners.
1.0 GENERAL INFORMATION
The Industrial I/O Pack (IP) Series IP1K100 module is a
reconfigurable digital input/output board. The IP1K100 contains a
100,000 gate Altera
Field Programmable Gate Array (FPGA)
which is in-system reconfigurable. This allows designers to
implement logic functions unique to their application and in-system
configure the Altera FPGA via the IP bus interface.
An example Altera FPGA configuration file and its
corresponding VHDL source are provided with the IP1K100
Engineering Design Kit. To take advantage of the example VHDL
program, the user must be proficient in the use of VHDL and the
Altera Maxplus II or Quartus software tools.
The IP1K100 provides several different interface options which
allow a mix of differential digital and TTL digital input/output
channels. The models and their corresponding combination of
channels are given in the table below.
Model
TTL Channels
EIA-485/422
Channels
IP1K100-0024
0
24
IP1K100-2412
24
12
IP1K100-4800
48
0
The IP1K100 can be programmed to support all types of IP
cycles at either 8 or 32 MHz operation. The IP1K100 comes with a
simple example Altera design file that can be enhanced for
implementation of custom digital logic functions.
