SERIES IP1K100 INDUSTRIAL I/O PACK RECONFIGURABLE DIGITAL I/O MODULE
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ENVIRONMENTAL
Operating Temperature.........… Standard Unit 0 to +70
°
C.
Relative Humidity...................... 5-95% Non-Condensing.
Storage Temperature................ -55
°
C to +125
°
C.
Non-Isolated....................…...... Logic and field commons have a
direct electrical connection.
Resistance to RFI.........…......... Complies with IEC1000-4-3 (3
V/m, 80 to 1000MHz AM &
900MHz. Keyed) and European
Norm EN50082-1 with no digital
upsets.
Electromagnetic Interference
Immunity (EMI)…...…..….....…. No register upsets under the
influence of EMI from switching
solenoids, commutator motors,
and drill motors.
Surge Immunity………………… Not required for signal I/O per
European Norm EN50082-1.
Electric Fast Transient
Immunity EFT………………….. Complies with IEC1000-4-4 Level
2 (0.5KV at field input and output
terminals) and European Norm
EN50082-1.
Radiated Emissions………...... Meets or exceeds European Norm
EN50081-1 for class A equipment.
Warning: This is a class A product. In a domestic environment
this product may cause radio interference in which the
user may be required to take adequate measures.
Model
TTL Channels
EIA-485 Channels
IP1K100-0024
0
24
IP1K100-2412
24
12
IP1K100-4800
48
0
EIA-RS485 TRANSCEIVERS
Channel Configuration……..…. Up to 24, non-isolated EIA
RS485/RS422 serial ports with a
common signal return connection.
Selected in blocks of 4 signal
pairs/channels when ordered.
Data Rate……………….……… 2.5M bits/sec, Maximum.
Cable Length………………..…. 4000 feet, Maximum. Use of a
signal repeater can extend
transmission distances beyond
this limit.
Termination Resistors…………. Termination Resistors are not
provided. Termination resistors
are recommended at network end
points only (see Drawing 4501-702
for location).
Differential Output Voltage…… 5V Maximum; 1.5V Minimum (with
27
Ω
load).
Common Mode Output
Voltage………………………….. 3V Maximum.
Output Short Circuit Current…. 250mA, Maximum.
Input Hysteresis……………..… 70mV (V
CM
=0V).
TTL TRANSCEIVERS
Channel Configuration……..…. Up to 48, non-isolated TTL
signals. Selected in blocks of 8
channels when ordered.
Integrated Circuit Device
Pericom PI74FCT623T
http://www.pericom.com/
INDUSTRIAL I/O PACK COMPLIANCE
Specification………….………… This device meets or exceeds all
written Industrial I/O Pack
specifications per ANSI/VITA 4
1995 for 8MHz or 32MHz
operation for Type I Modules.
Electrical/Mechanical
Interface………………….……... Single-Size IP Module.
I/O Space...................…....…... 16-bit and 8-bit:
ID Space...................…........…. 16 and 8-bit; Supports Type 1, 32
bytes per IP (consecutive odd byte
addresses). IPAH is used to
indicate 32MHz operation (8MHz
operation is also supported).
Memory Space....................….
Supported by hardware but not
implemented in example design.
Interrupts……................……… Generates INTREQ0
∗
interrupt
request per IP and interrupt
acknowledge cycles via access to
IP INT space.
INTREQ1
∗
available but not driven
by example FPGA design.
DMA………………………………Two IP request levels available but
not implemented in example FPGA
design.
Interrupts:
Handling Format………….……. An 8-bit vector is provided during
interrupt acknowledge cycles on
data lines D0…D7. The release
mechanism is RORA type
(Release On Register Access).
FPGA
FPGA……………………………. Altera EP1K100QC208-1
100K typical gates and 49,152
RAM bits
IP1K100 Engineering Design Kit
Model IP-1K100-EDK………….. Engineering design kit provides the
user with the basic information
required to develop a custom
FPGA program for download to the
Altera FPGA. The design kit
includes a CD containing:
schematics, parts list, part location
drawing, example VHDL source,
example configuration file, and
other utility files. The IP1K100 is
intended for users fluent in the use
of Altera MaxPlus II or Quartus
design tools.
NineK453a.hex …………………. Hexadecimal (Intel-Format)
configuration file. The Hex file is
an ASCII file in the Intel Hex
format. The file is generated by
the Altera software and is used to
program the Altera FPGA over the
IP bus interface.
NineK453a.vhd…..….…..……… Acromag provided VHDL
(hardware design language)
source file supports IP bus
interface to ID, IO, and INT space.
