AXM-VFX-EDK User’s Manual Mezzanine Board
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Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:[email protected] http://www.acromag.com
15
Interrupt Polarity Register (Read/Write) –
(P 801C)
The Interrupt Polarity Register determines the level that will cause a
channel interrupt to occur for each of the channels enabled for level
interrupts. A “0” bit specifies that an interrupt will occur when the
corresponding input channel is low (i.e. a “0” in the differential input channel
data register). A “1” bit means that an interrupt will occur when the input
channel is high (i.e. a “1” in the differential input channel data register).
Note that no interrupts will occur unless they are enabled by the Interrupt
Enable Register. Further, the Interrupt Polarity Register will have no effect if
the Change-of-State (COS) interrupt type is configured by the Interrupt Type
Configuration Register.
The Interrupt Polarity register at the P offset 801CH is used to
control differential channels 8 through 15 as mapped in the Interrupt Enable
Register. For example, channel 8 is controlled via data bit-0. Bits 8 to 15
are not used and will always read as “0”.
All bits are set to “0” following a reset, which means that the inputs will
cause interrupts when they are logic low (provided they are enabled for
interrupt on level).