Acromag APC8620 Series User Manual Download

Page: 10 / 21

INDUSTRIAL I/O PACK SERIES APC8620/8621 PCI BUS CARRIER BOARD
___________________________________________________________________________________________

- 9 -

IP Module I/O Space - (Read/Write Only, 256-Byte Addresses)

The I/O space on each IP module is fixed at 128, 16-bit

words (256 bytes). The five (three for APC8621) IP module I/O
spaces are accessible at fixed offsets for the APC8620/8621’s
Base Address. IP modules may not fully decode their I/O space
and may use byte or word only accesses. See each IP module’s
User Manual for details.

GENERATING INTERRUPTS

Interrupt requests originate from the carrier board in the case

of an access time out and from the IP modules. Each IP may
support 0, 1, or 2 interrupt requests. Upon an IP module interrupt
request the carrier passes the interrupt request onto the host,
provided that the carrier board is enabled for interrupts within the
Carrier Board Status Register.

Sequence of Events For an Interrupt

1. Clear the interrupt enable bits in the Carrier Board Status

2. Write interrupt vector to the location specified on the IP and

perform any other IP specific configuration required - do for
each supported IP interrupt request.

3. Determine the IRQ line assigned to the carrier during

system configuration (within the configuration register).

4. Set up the PC/AT’s interrupt vector for the appropriate

interrupt.

5. Unmask the IRQ on the PC/AT’s 8259 interrupt controller.
6. The IP asserts an interrupt request to the carrier board

(asserts interrupt request line IntReq0* or IntReq1*).

7. The carrier drives PCI bus interrupt request signal INTA#

active.

8. PC/AT’s drives the IRQ line assigned to the active carrier.
9. The interrupt service routine pointed to by the vector set up

in step 4 starts.

10. Interrupt service routine determines which IP module caused

the interrupt by reading the carrier interrupt pending register.
If multiple interrupts are pending the interrupt service routine
software determines which IP module to service first. In a
PC interrupts are shared and can be from any slot on the
backplane or from the mother board itself. The driver must
first check that the interrupt came from the PCI carrier by
reading the carrier interrupt pending register.

11. The interrupt service routine accesses the interrupt space of

the IP module selected to be serviced. Note that the
interrupt space accessed must correspond to the interrupt
request signal driven by the IP module.

12. The carrier board will assert the INTSEL* signal to the

appropriate IP together with (carrier board generated)
address bit A1 to select which interrupt request is being
processed (A1 low corresponds to INTREQ0*; A1 high
corresponds to INTREQ1*).

13. The IP module receives an active INTSEL* signal from the

carrier and supplies its interrupt vector to the host system
during this interrupt acknowledge cycle. An IP module
designed to release its interrupt request on acknowledge will
release its interrupt request upon receiving an active
INTSEL* signal from the carrier. If the IP module is
designed to release it’s interrupt request on register access
the interrupt service routine must access the required
register to clear the interrupt request.

14. Write “End-Of-Interrupt” command to PC/AT’s 8259.
15. If the IP interrupt stimulus has been removed and no other

IP modules have interrupts pending, the interrupt cycle is
completed (i.e. the carrier board negates its interrupt request
INTA#).

4.0 THEORY OF OPERATION

This section describes the basic functionality of the circuitry

used on the carrier board. Refer to the Block Diagram shown in
the Drawing 4501-673 as you review this material.

CARRIER BOARD OVERVIEW

The carrier board is a PCI bus slave/target board providing up

to five (three for APC8621) industry standard IP module
interfaces. The carrier board’s PCI bus interface allows an
intelligent single board computer (PCI bus Master) to control and
communicate with IP modules that are present on the PCI bus
carrier. IP module field I/O connections link to the field I/O
connections of the carrier which in turn are used to connect field
electronic hardware to the carrier board via ribbon cable.

The PCI bus and IP module logic commons have a direct

electrical connection (i.e., they are not electrically isolated).
However, the field I/O connections can be isolated from the PCI
bus if an IP module that provides this isolation (between the logic
and field side) is utilized. A wide variety of IP modules are
currently available (from Acromag and other vendors) that allow
interface to many external devices for digital I/O, analog I/O, and
communication applications.

PCI Bus Interface

The carrier board’s PCI bus interface is used to program and

monitor carrier board registers for configuration and control of the
board’s documented modes of operation (see section 3). In
addition, the PCI bus interface is also used to communicate with
and control external devices that are connected to an IP module’s
field I/O signals (assuming an IP module is present on the carrier
board).

The PCI bus interface is implemented in the logic of the

carrier board’s PCI bus target interface chip. The PCI bus
interface chip implements PCI specification version 2.1 as an
interrupting slave including 8-bit and 16-bit data transfers to the
IP modules.

The carrier board’s PCI bus data transfer rates are shown in

Table 2.3.

Carrier Board Registers

The carrier board registers (presented in section 3) are

implemented in the logic of the carrier board’s FPGA. An outline
of the functions provided by the carrier board registers includes:

•

Monitoring the error signal received from each IP module is
possible via the IP Error Bit.

•

Enabling of PCI bus interrupt requests from each IP module
is possible via the IP Module Interrupt Enable Bit.

•

Enabling of interrupt generation upon an IP module access
time out is implemented via the Time Out Interrupt Enable
Bit.

•