INDUSTRIAL I/O PACK SERIES APC8620/8621 PCI BUS CARRIER BOARD
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IP module D and E field connectors (as shown in Drawing 4501-
671). On the APC8621 the Strobe signals for each of the three
IP modules are routed on the printed circuit board to the location
just above of IP module C field connector (as shown in Drawing
4501-676). The factory default is to leave these signals
unconnected.
Table 2.1: Standard IP Logic Interface Connections
Pin Description
Number
Pin Description
Number
GND
1
GND
26
CLK
2
+5V
27
Reset*
3
R/W*
28
D00
4
IDSEL*
29
D01
5
DMAReq0*
30
D02
6
MEMSEL*
31
D03
7
DMAReq1*
32
D04
8
IntSel*
33
D05
9
DMAck0*
34
D06
10
IOSEL*
35
D07
11
RESERVED
36
D08
12
A1
37
D09
13
DMAEnd*
38
D10
14
A2
39
D11
15
ERROR*
40
D12
16
A3
41
D13
17
INTReq0*
42
D14
18
A4
43
D15
19
INTReq1*
44
BS0*
20
A5
45
BS1*
21
STROBE*
46
-12V
22
A6
47
+12V
23
ACK*
48
+5V
24
RESERVED
49
GND
25
GND
50
Asterisk (*) is used to indicate an active-low signal.
BOLD ITALIC Logic Lines are NOT USED by the carrier board.
PCI Bus Connections
Table 2.2 indicates the pin assignments for the PCI bus
signals at the card edge connector. Connector pins are
designated by a letter and a number. The letter indicates which
side of a particular connector the pin contact is on. “B” is on the
component side of the carrier board while “A” is on the solder
side. Connector “gold finger” numbers increase with distance
from the bracket end of the printed circuit board.
Refer to the PCI bus specification for additional information
on the PCI bus signals.
TABLE 2.2: PCI Bus P1 CONNECTIONS
Signal
Pin
Pin
Signal
-12V
B01
A01
TRST#
TCK
B02
A02
+12V
Ground
B03
A03
TMS
TDO
B04
A04
TDI
+5V
B05
A05
+5V
+5V
B06
A06
INTA#
INTB#
B07
A07
INTC#
INTD#
B08
A08
+5V
PRSNT1#
B09
A09
Reserved
Reserved
B10
A10
+5V
PRSNT2#
B11
A11
Reserved
Signal
Pin
Pin
Signal
Ground
B12
A12
Ground
Ground
B13
A13
Ground
Reserved
B14
A14
Reserved
Ground
B15
A15
RST#
CLK
B16
A16
+5V
Ground
B17
A17
GNT#
REQ#
B18
A18
Ground
+5V
B19
A19
Reserved
AD[31]
B20
A20
AD[30]
AD[29]
B21
A21
+3.3V
Ground
B22
A22
AD[28]
AD[27]
B23
A23
AD[26]
AD[25]
B24
A24
Ground
+3.3V
B25
A25
AD[24]
C/BE[3]#
B26
A26
IDSEL
AD[23]
B27
A27
+3.3V
Ground
B28
A28
AD[22]
AD[21]
B29
A29
AD[20]
AD[19]
B30
A30
Ground
+3.3V
B31
A31
AD[18]
AD[17]
B32
A32
AD[16]
C/BE[2]#
B33
A33
+3.3V
Ground
B34
A34
FRAME#
IRDY#
B35
A35
Ground
+3.3V
B36
A36
TRDY#
DEVSEL#
B37
A37
Ground
Ground
B38
A38
STOP#
LOCK#
B39
A39
+3.3V
PERR#
B40
A40
SDONE
+3.3V
B41
A41
SBO#
SERR#
B42
A42
Ground
+3.3V
B43
A43
PAR
C/BE[1]#
B44
A44
AD[15]
AD[14]
B45
A45
+3.3V
Ground
B46
A46
AD[13]
AD[12]
B47
A47
AD[11]
AD[10]
B48
A48
Ground
Ground
B49
A49
AD[09]
KEYWAY
KEYWAY
KEYWAY
KEYWAY
AD[08]
B52
A52
C/BE[0]#
AD[07]
B53
A53
+3.3V
+3.3V
B54
A54
AD[06]
AD[05]
B55
A55
AD[04]
AD[03]
B56
A56
Ground
Ground
B57
A57
AD[02]
AD[01]
B58
A58
AD[00]
+5V
B59
A59
+5V
ACK64#
B60
A60
REQ64#
+5V
B61
A61
+5V
+5V
B62
A62
+5V
(#) s used to indicate an active-low signal.
BOLD ITALIC Logic Lines are NOT USED by the carrier board.
DATA TRANSFER TIMING
All PCI bus read or write cycles to the APC8620/8621 are
typically implemented within 150n seconds (FRAME# active to
TRDY# active). After 150n seconds the PCI bus is available to
the system for other PCI bus activity. As the PCI bus is released,
the APC8620/8621 completes the read or write cycle to the
targeted IP module or carrier register within the access times
given in Table 2.3.
Bracket End
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