AP513 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 28 -
http://www.acromag.com
- 28 -
www.acromag.com
3.4.1 Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and
Receive Holding Register (RHR). The RSR uses the 16X, 8X or 4X clock for
timing. It verifies and validates every bit on the incoming character in the
middle of each data bit. On the falling edge of a start or false start bit, an
internal receiver counter starts counting at the 16X, 8X or 4X clock rate.
After 8 or 4 or 2 clocks the start bit period should be at the center of the
start bit. At this time the start bit is sampled and if it is still a logic 0 it is
validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there
were any error(s), they are reported in the LSR register bits [4:1]. Upon
unloading the receive data byte from RHR, the receive FIFO pointer is
bumped and the error flags are immediately updated to reflect the status of
the data byte in RHR register. RHR can generate a receive data ready
interrupt upon receiving a character or delay until it reaches the FIFO trigger
level. Furthermore, data delivery to the host is guaranteed by a receive data
ready time-out function when receive data does not reach the receive FIFO
trigger level. This time-out delay is 4 word lengths as defined by LCR bits
[1:0] plus 12 bits time. The RHR interrupt is enabled by IER bit [0].
3.4.2 Transmitter
The transmitter section comprises of a 256 byte FIFO, a byte-wide Transmit
Holding Register (THR) and an 8-bit Transmit Shift Register (TSR). THR
receives a data byte from the host (non-FIFO mode) or a data byte from the
FIFO when the FIFO is enabled by FCR bit [0]. TSR shifts out every data bit
with the 16X or 8X internal clock. A bit time is 16 or 8 clock periods. The
transmitter sends the start bit followed by the number of data bits, inserts
the proper parity bit if enable, and adds the stop bit(s). The status of the
THR and TSR are reported in the Line Status Register (LSR bit [6:5]).
3.4.2.1 Transmit Holding Register (THR)
The transmit holding register is an 8-bit register providing a data interface to
the host processor. The host writes transmit data byte to the THR to be
converted into a serial data stream including start-bit, data bits, parity-bit
and stop-bit(s). The least-significant-bit (bit [0]) becomes first data bit to go
out. The THR is also the input register to the transmit FIFO of 256 bytes
when FIFO operation is enabled by FCR bit[0]. A THR empty interrupt can be
generated when it is enabled in IER bit [1].
3.4.2.2 Transmitter Operation in non-FIFO mode
The host loads transmit data to THR one character at a time. The THR empty
flag (LSR bit [5]) is set when the data byte is transferred to TSR. THR flag can
generate a transmit empty interrupt (ISR bit [1]) when it is enabled by IER
bit [1]. The TSR flag (LSR bit [6]) is set when TSR becomes completely empty.
