Acromag 948 Series, User Manual

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AVME948x USER'S MANUAL Digital I/O Board
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The VME Control Logic
The VME control logic takes care of the Data Transfer
Acknowledge (DTACK*) timing and the Bus Error (BERR*) logic.
The Digital I/O Board will assert the VME BERR* signal if the host
CPU tries to access the card using a long-word read or write data
transfer. U57 and U43 control the DTACK* timing. The transfer
ackowledge delay signal (DDLAY) is asserted when the card has
been properly decoded and either of the data strobes (DS1*, DS0*)
are asserted. This allows U43 to start shifting a logical "1" across
its outputs. The delay time is programmed by the factory through
jumper J18. When DTACK is asserted, it is inverted through U42
and the VME DTACK* signal is asserted.
The VME Interrupter
The VME interrupter block diagram is shown in Drawing
4500-740. Refer to the schematic and parts location Drawing
4500-737 for the items referenced in the following paragraphs.
The VME interrupter on the Digital I/O card is a Release on
Register Access (RORA) type interrupter and will return an eight bit
vector during the interrupt acknowledge cycle. The RORA type
interrupter will release the interrupt request line (IRQx*) after the
interrupt has been cleared. The interrupter logic contains a
programmable interrupt level accessible through the Interrupt Level
Register.
The eight I/O interrupt points are level sensitive and work on a
first come, first serve basis, unless the interrupts occur at the same
time. If two or more interrupts occur at the same time, then I/O
interrupt point 7 has the highest priority with I/O interrupt point 0
having the lowest priority. Each I/O interrupting point may be
programmed with its own interrupt vector. Also, each I/O interrupt
point may be individually masked, and the polarity may be selected.
The Interrupt Vector Register is contained in U30. U15 is the
Interrupt Enable Register. The Enable Register is read through U9
and U10. U28 is the Interrupt Polarity Register.
When the I/O interrupt inputs sense the proper level on one of
the I/O interrupt points of Port 0 the interrupter logic will assert the
pre-programmed interrupt request level (IRQ7* - IRQ1*) and then
monitor the Interrupt Acknowledge Input (IACKIN*) line. When the
IACKIN* is asserted, the logic compares the VME address lines A1,
A2, and A3 to the pre-programmed interrupt level. If the lines are not
equal, it will pass the signal along by asserting IACKOUT*. If the
lines are equal, it will then drive the data bus with the vector
associated with the I/O interrupting point and assert the DTACK*
signal. U53 controls the interrupt request level decoding. U61
contains the Interrupt Level Register and controls all VME interrupt
interface signals. U25 senses an incoming interrupt request from
the I/O interrupt point(s), enables U53, selects the proper address
for the interrupt vector RAM, and will give priority to simultaneous
interrupt requests. The Interrupt Pending Register is U11 and U12.
The Interrupt Inputs Register is contained in U26 and U27. Both the
Interrupt Pending and Interrupt Inputs Register are read through
U13 and U14.
DIGITAL I/O PORT REGISTERS (READ/WRITE)
The I/O Port Registers reflect and/or control the state of the
bidirectional I/O points. Points are grouped eight to a port. To use a
point as an input, first write a "0" to it to cause the open-collector
output driver to go into an OFF (high impedance) state. That lets the
point be pulled to a high voltage level by an onboard pull-up resistor.
The point may then be driven by an external device. Reading the
point will reflect the INVERTED level at the I/O connector.
To use a point as an output, write "1" or "0" to the point as desired.
If the point is read, it will reflect the state of the output as well. Note
that because inverted logic is used, a high level at the I/O connector
is read as "0" in the port register, and a low level is read as a "1".
This is consistent with the use of open-collector outputs to drive
relays and switches. A logic "1" in the computer produces a low
level at the output driver to "pull in" a relay or turn something "on".
Input Comparators/Buffers
Analog voltage comparators are used as input devices to allow
the inputs to withstand up to 30V (see Drawing 4500-742). During
normal operation, REF is held at +5V which establishes a reference
voltage of approximately 1.8 volts from voltage divider R23 & R24,
which appears at the inverting inputs of all the comparators for that
group. Resistors R21 and R22 along with comparator U8 form a
hysteresis switch with a lower threshold of 1V and an upper
threshold of 2.2V. Buffer U38 is used to put the comparator outputs
for the port on the data bus during read operations.
Output Latches/Drivers
(Refer to Drawing 4500-742 for the following discussion)
Output latch/driver U52 contains 8 CMOS latches and 8 open-
collector darlington transistors. Removable resistor network R57
provides pullup for the I/O lines and is usually pulled up to +5V on
the card through jumper J7. Each output has a protection diode, Dp
which is usually tied to the relay supply voltage when driving relay
coils. This diode clamps the high voltage spike (reverse emf) that
can occur when a relay coil is turned off quickly.
5.0 SERVICE AND REPAIR INFORMATION
This section provides calibration procedures, service diagrams
and instructions on how to obtain service and repair assistance.
SERVICE AND REPAIR ASSISTANCE
It is highly recommended that a non-functioning board be
returned to Acromag for repair. Acromag uses tested and burned-in
parts, and in some cases, parts that have been selected for
characteristics beyond that specified by the manufacturer. Further,
Acromag has automated test equipment that thoroughly checks the
performance of each board. When a board is first produced and
when any repair is made, it is fully tested, placed in a burn-in room at
elevated temperature, and then retested before shipment. Please
refer to Acromag's Service Policy Bulletin or contact Acromag for
complete details on how to obtain parts and repair.
PRELIMINARY SERVICE PROCEDURE
Before attempting calibration or repair, be sure that all of the
procedures in Section 2 (Preparation For Use) have been followed.
These procedures are necessary since the board has jumpers that
must be properly configured.
Note: It has been observed that on occassion, a "boot" program for
a disk operating system will "hang" waiting for the VMEbus
SYSFAIL* signal to be released by an intelligent disk controller
board. Acromag's non-intelligent slave boards assert the SYSFAIL*
signal as described to the VMEbus Specification, and therefore, the
disk operating system will remain "hung". The best solution to this
problem is to correct the boot program so that it is no longer
dependent upon the SYSFAIL* signal. When this solution is not
practical, it is possible to disconnect the SYSFAIL* from the circuitry
on the Acromag board by removing the jumper for J20.
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