1 -
1
5
1 -
1
5
1 -
1
5
1 -
1
5
1 -
1
5
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
DRAM Clock
This item determines DRAM Clock following the CPU
host clock.
The Choices: By SPD
(default), 100.
DRAM Timing
The DRAM timing is controlled by the DRAM Timing
Registers. The Timings programmed into this register are
dependent on the system design.
The Choices: By SPD
(default), Manual.
SDRAM CAS Latency
2.5 (default)
Set SDRAM latency Time to
2.5.
2
Set SDRAM latency Time to 2.
Bank Interleave
The Choices: Disabled
(default), 2 Bank, 4 Bank.
Precharge to Active (Trp)
The Choices: 3T
(default), 2T.
Active to Precharge
6T (default)
Set DRAM Precharge in 6.
5T
Set DRAM Precharge in 5.
Active to CMD (Trcd)
The Choices: 3T
(default), 2T.
DRAM Queue Depth
The Choices: 4 Level
(default), 2 Level, 3 Level.
DRAM Command Rate
The Choices: 2T Command
(default), 1T Command.