1 -
1
7
1 -
1
7
1 -
1
7
1 -
1
7
1 -
1
7
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
AGP Master 1WS Read
When Enabled, read data to the AGP (Accelerated Graphic
Port) that will be executed with one wait states.
The Choices: Disabled
(default), Enabled.
CMOS Setup Utility-Copyright (C) 1984-2001 Award Software
CPU & PCI Bus Control
PCI 1 Master 0 WS Write
Enabled
Item Help
PCI 2 Master 0 WS Write
Enabled
PCI 1 Port Write
Enabled
Menu Level
PCI 2 Port Write
Enabled
PCI Delay Transaction
Disabled
←→↑↓
: Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F1:General Help F5:Previous Values F6:Fail-Safe Defaults
F7:Optimized Defaults
PCI 1 Master 0 WS Write
When this field is Enabled, write data to the PCI bus are
executed with zero wait states.
The Choices: Enabled
(default), Disabled.
PCI 2 Master 0 WS Write
When this field is Enabled, write data to the PCI bus are
executed with zero wait states.
The Choices: Enabled
(default), Disabled.
PCI 1 Port Write
The Choices: Enabled
(default), Disabled.
PCI 2 Port Write
The Choices: Enabled
(default), Disabled.
PCI Delay Transaction
The Choices: Disabled
(default), Enabled.