1 -
1
5
1 -
1
5
1 -
1
5
1 -
1
5
1 -
1
5
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
Bhapter 1
B
IOS Set
t
p
Bank 0/1,2/3,4/5 DRAM Timing
This item allows you to select the value in this field,
depending on whether the board has paged DRAMs or EDO
(extended data output)DRAMs.
The Choices:
8/10ns
(default), EDO 50ns, EDO 60ns,
Slow, Medium, Fast, Turbo.
DRAM Clock
This item determines DRAM Clock following the CPU
host clock,or .
The Choices: Host CLK
(default), Host CLK+33M, Host
CLK-33M.
SDRAM Cycle Length
When synchronous DRAM is installed, the number of
clock cycle of CAS latency depends on the DRAM timing.
Do not reset this field from the default value specified by
the system designer.
The Choices: 3
(default), 2, Auto.
Bank Interleave
The Choices: Disabled
(default), Enabled.
Memory Hole
In order to improve performace, certain space in memory
can be reserved for ISA cards. This memory must be
mapped into the memory's space below 16MB.
The Choices: Diasbled
(default), Enabled.
P2C/C2P Concurrency
The item allows you to enable/disable the PCI to CPU to
PCI concurrency.
The Choices: Enabled
(default), Disabled.
System BIOS Cacheable
When enabled, the access to the system BIOS ROM
address at F0000H-FFFFFFH is cached.
The Choices: Diasbled
(default), Enabled.
