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Chapter 2
BIOS Setup
AGP Master 1WS Write
AGP Master 1WS Read
Phoenix-Award WorkstationBIOS CMOS Setup Utility
CPU & PCI Bus Control
CPU to PCI Write Buffer
Enabled
PCI Master 0 WS Write
Enabled
PCI Delay Transaction
Disabled
VLink 8X Support
Disabled
←→↑↓
: Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F1:General Help F5:Previous Values F6:Fail-Safe Defaults
F7:Optimized Defaults
CPU to PCI Write Buffer
PCI Master 0 WS Write
PCI Delay Transaction
The Choices: Disabled(default), Enabled.
VLink 8X Support
The Choices: Disabled(default), Enabled.
When Enabled, write data to the AGP (Accelerated Graphic
Port) that will be executed with one wait states.
The Choices: Disabled(default), Enabled.
When Enabled, read data to the AGP (Accelerated Graphic
Port) that will be executed with one wait states.
The Choices: Disabled(default), Enabled.
When this field is Enabled, write from the CPU to the PCI bus
are buffered, to compensate for the speed differences
between the CPU and the PCI bus. When Disabled, the are
not buffered and the CPU must wait until the write is complete
before starting another write cycle.
When this field is Enabled, write data to the PCI bus are
executed with zero wait states.
The Choices: Enabled(default), Disabled.
Menu Level
Item Help
