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142
Chapter 4
0x7E
The Coprocessor initialization test. Use the floating point
instructions to determine if a coprocessor exists instead of the
ET bit in CR0.
LBT
Core
0xC1
Check Boot Type (Server BIOS)
LBT
Core
0x80
Disable onboard COM and LPT ports before testing for
presence of external I/O devices.
LBT
Core
0xCA
Redirect Int 15h to enable target board to use remote keyboard
(PICO BIOS).
LBT
Core
0x88
Initialize interrupt controller.
LBT
Core
0x81
Run late device initialization routines.
LBT
Core
0x87
Initialize motherboard configurable devices.
LBT
Core
0x85
Display any ESCD read errors and configure all PnP ISA
devices.
LBT
Core
0x82
Test and identify RS232 ports.
LBT
Core
0x84
Test and identify parallel ports.
LBT
Core
0x86
Initialize onboard I/O and BDA according to CMOS and
presence of external devices.
LBT
Core
0x83
Configure Fisk Disk Controller.
LBT
Core
0xCE
Initialize digitizer device and display installed message if
successful.
LBT
Core
0x89
Enable non-maskable interrupts.
LBT
Core
0x8C
Initialize both of the floppy disks and display an error message
if failure was detected. Check both drives to establish the
appropriate diskette types in the TrustedCore data area
LBT
Core
0xCB
Redirect Int 13h to Memory Technologies Devices such as
ROM, RAM, PCMCIA, and serial disk (PICO BIOS).
LBT
Core
0xCD
Remap I/O and memory address space for PCMCIA (PICO
BIOS).
LBT
Core
0x90
Initialize hard-disk controller. If the CMOS ram is valid and
intact, and fixed disks are defined, call the fixed disk init routine
to initialize the fixed disk system and take over the appropriate
interrupt vectors.
LBT
Core
0x8B
Setup interrupt vector and present bit in Equipment byte.
LBT
Core
0x95
1. Check CMOS for CD-ROM drive present
2. Activate the drive by checking for media present
3. Check sector 11h (17) for Boot Record Volume Descriptor
4. Check the boot catalog for validity
5. Pick a boot entry
6. Create a Specification Packet
LBT
Core
0x92
Jump to UserPatch2.
LBT
Core
0xB6
If password on boot is enabled, a call is made to Setup to
check password. If the user does not enter a valid password,
Setup does not return.
LBT
Core
0x98
Search for option ROMs. Rom scan the area from C800h for a
length of BCP_ROM_Scan_Size (or to E000h by default) on
every 2K boundary, looking for add on cards that need
initialization.
LBT
Core
0x93
Build the MPTABLE for multi-processor boards
LBT
Core
POST
Code
Function
Phase
Component
Summary of Contents for LX.AUQ0X.080 - Aspire 6530-5195 - Athlon X2 1.9 GHz
Page 6: ...VI ...
Page 10: ...X Table of Contents ...
Page 14: ...4 Chapter 1 System Block Diagram ...
Page 50: ...40 Chapter 2 ...
Page 85: ...Chapter 3 75 4 Grasp the module by the right side and lift up to remove ...
Page 93: ...Chapter 3 83 7 Disconnect the Mic cable and remove the LCD bezel ...
Page 104: ...94 Chapter 3 4 Replace the ten securing screws and screw caps on the LCD bezel ...
Page 106: ...96 Chapter 3 3 Connect fan cable to the mainboard as shown ...
Page 111: ...Chapter 3 101 2 Reconnect the TouchPad and Finger Print Reader FFCs as shown ...
Page 120: ...110 Chapter 3 7 Turn the computer over and replace the ten screws as shown ...
Page 155: ...Chapter 5 145 Jumper and Connector Locations Top View Chapter 5 ...
Page 156: ...146 Chapter 5 Bottom View ...
Page 173: ...Chapter 6 163 ...
Page 220: ...210 Appendix B ...
Page 222: ...212 Appendix C ...