Sharing Interrupts on the ISA Bus
On occasion a system application will require more interrupt levels than are available on the ISA bus.
While this is not recommended, IRQ sharing is possible. Each board that is going to share an IRQ must
strictly adhere to a special standard for accessing the IRQ lines as follows:
1.
The interrupt must be held in a high impedance state until asserting an interrupt.
2.
The interrupt must be asserted in the form of a low signal lasting at least 500 nanoseconds followed by
a rising edge and then immediately returning to a high impedance condition.
3.
The board must contain a status register or flag of some kind to indicate that it generated the interrupt.
There is an exception to this rule. This is the case where only one board (of those sharing the interrupt
level) does not provide a status bit to indicate that it asserted the interrupt but is otherwise capable of
sharing the IRQ. In this case, it may share the interrupt level with other boards if (a) it is the only board
on that IRQ level that does not have a status bit and (b) it is installed onto the IRQ vector first. (This
makes it the last board to be called in the vector chain.) This scheme will work because it can be
assumed that if every other board in the vector chain did not cause the interrupt, then the last board
must be the one that did.
Note
If two boards assert the IRQ line within 500 nanoseconds of each other, the second board in the ISR chain will
not be serviced. It is possible to alleviate this problem by writing a single ISR that can detect the bit flag on
every board and therefore detect the fact that two boards (or more) report generating an interrupt even though
only one interrupt was processed by the CPU.
The interrupt driver circuit on the board will drive the selected IRQ line for approximately 500nS and then tri-
state.
Manual 104-DIO-48E, 24E
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