Abit NF-95, Installation Manual

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DRAM Configuration
Click <Enter> key to enter its submenu:
DRAM Timing Selectable
This item sets the optimal timings for the following four items, depending on the memory
module you are using. The default setting “By SPD” configures these four items by reading the
contents in the SPD (Serial Presence Detect) device. The EEPROM on the memory module
stores critical parameter information about the module, such as memory type, size, speed,
voltage interface, and module banks.
- DRAM Clock
This item controls the number of DRAM clocks used for the DRAM parameters.
- CAS Latency Time
This item controls the latency between the DRAM read command and the time that the data
becomes actually available.
- Min RAS# Active Time
This item specifies the minimum RAS# active time.
- RAS# to CAS# Delay
This item controls the latency between the DRAM active command and the read/write
command.
- RAS# Precharge Time
This item controls the idle clocks after issuing a precharge command to the DRAM.
User Config mode
This item manually sets the DRAM configuration or controlled by BIOS.
- 1T/2T Memory Timing
This item manually specifies the DRAM memory time mode.
- Read Preamble value
This item manually specifies the DRAM read preamble value.
3-8 NF-95