2-8
A-S78H
2.4 Advanced Chipset Features
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
►
DRAM Configuration
Press Enter
Item Help
►
HT Link Control
Press Enter
►
PCIe Configuration
Press Enter
►
IGX Configuration
Press Enter
Init Display First
PCIe
TLB Cache Function
Disabled
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
DRAM Configuration
Click <Enter> key to enter its submenu.
You may manually set the DRAM timing parameters through its sub-items, or leave them at
their default settings according to the SPD (Serial Presence Detect) data stored in the DRAM.
HT Link Control
Click <Enter> key to enter its submenu. You may manually set the parameters through each
sub-item, or leave them at their default settings.
Phoenix – AwardBIOS CMOS Setup Utility
HT Link Control
HT Link Width
Auto
Item Help
HT Link Frequency
Auto
HT Link Tristate
Auto
UnitID Clumping
Auto
2x LCLK Mode
Disabled
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
