91
Scheme communication logic for residual
overcurrent protection (EFC)
Chapter 10
Verifying settings by secondary
injection
15
Scheme communication logic for residual
overcurrent protection (EFC)
Prepare the terminal for verification of settings as outlined in section “Preparing for
test” in this chapter. Before testing the communication logic for residual overcurrent
protection, the time delayed residual overcurrent protection has to be tested according
to the corresponding instruction. Then continue with the instructions below.
If the current reversal and weak-end-infeed logic for earth-fault protection is included,
proceed with the testing according to the corresponding instruction after the test of the
communication logic for residual overcurrent protection. The reversal current and
weak-end-infeed functions shall be tested together with the permissive scheme.
15.1
Testing the directional comparison logic function
15.1.1
Blocking scheme
Procedure
1.
Inject the polarising voltage 3U0 to 5% of Ub and the phase
angle between voltage and current to 65°, the current lagging
the voltage.
2.
Inject current (65° lagging the voltage) in one phase to about
110% of the setting operating current, and switch off the cur-
rent with the switch.
3.
Switch on the fault current and measure the operating time of
the EFC logic.
Use the EFC--TRIP signal from the configured binary output to
stop the timer.
4.
Compare the measured time with the set value tCoord.
5.
Activate the EFC--CR binary input.
6.
Check that the EFC--CRL output is activated when EFC--CR
input is activated.
7.
Switch on the fault current (110% of the setting) and wait long-
er than the set value tCoord.
No EFC--TRIP signal should appear.
8.
Switch off the fault current.
9.
Reset the EFC--CR binary input.
10. Activate the EFC--BLOCK digital input.
