ABB ACS880-x04, Firmware Manual

Page: 403 / 604

Parameters 403
Auto falling One of the above modes is selected automatically depending
on the pulse frequency as follows: 5
92.12 Zero pulse enable (Visible when an absolute encoder is selected)
Enables the encoder zero pulse for the absolute encoder input
(X42) of the FEN-11 interface module.
Note: No zero pulse exists with serial interfaces, ie. when
parameter 92.11 Absolute position source is set to EnDat ,
Hiperface , SSI or Tamagawa .
Disable
Disable Zero pulse disabled. 0
Enable Zero pulse enabled. 1
92.12 Resolver polepairs (Visible when a resolver is selected)
Defines the number of pole pairs of the resolver.
1
1…32 Number of resolver pole pairs. 1 = 1
92.13 Position estimation
enable (Visible when a TTL, TTL+ or HTL encoder is selected)
Selects whether position estimation is used with encoder 1 to
increase position data resolution or not.
Enable
Disable Measured position used. (The resolution is 4 × pulses per
revolution for quadrature encoders, 2 × pulses per revolution
for single-track encoders.) 0
Enable Estimated position used. (Uses position interpolation;
extrapolated at the time of data request.) 1
92.13 Position data width (Visible when an absolute encoder is selected)
Defines the number of bits used to indicate position within one
revolution. For example, a setting of 15 bits corresponds to
32768 positions per revolution.
The value is used when parameter
92.11 Absolute position
source is set to EnDat , Hiperface or SSI . When parameter
92.11 Absolute position source is set to Tamagawa , this
parameter is internally set to 17.
Note: With an EnDat or HIPERFACE encoder and FEN-11
FPGA version VIE12200 or later, this parameter is
automatically set upon validation of encoder settings (
91.10
Encoder parameter refresh ).
0
0…32 Number of bits used in position indication within one
revolution. 1 = 1
92.14 Speed estimation
enable (Visible when a TTL, TTL+ or HTL encoder is selected)
Selects whether calculated or estimated speed is used.
Estimation increases the speed ripple in steady state
operation, but improves the dynamics.
Note: This parameter is not effective with FEN-xx modules
with FPGA version VIEx 2000 or later.
Disable
Disable Last calculated speed used. (The calculation interval is 62.5
microseconds to 4 milliseconds.) 0
Enable Estimated speed (estimated at the time of data request) is
used. 1
No. Name/Value Description Def / FbEq16
Pulse frequency of the
channel(s)
Used mode
< 2442 Hz A&B all
2442…4884 Hz A all
> 4884 Hz A falling