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bdi

GDB

for GNU Debugger, BDI2000 (ARM)

User Manual

33

© Copyright 1997-2005 by ABATRON AG Switzerland

V 1.17

ERASE addr [mode [wait]]The flash memory may be individually erased or unlocked via the Telnet

interface. In order to make erasing of multiple flash sectors easier, you can
enter an erase list. All entries in the erase list will be processed if you enter
ERASE at the Telnet prompt without any parameter. This list is also used
if you enter UNLOCK at the Telnet without any parameters.

address

Address of the flash sector, block or chip to erase

mode

BLOCK, CHIP, UNLOCK
Without this optional parameter, the BDI executes a sec-
tor erase. If supported by the chip, you can also specify
a block or chip erase. If UNLOCK is defined, the entry is
also part of the unlock list. This unlock list is processed
if the Telnet UNLOCK command is entered without any
parameters.

wait

The wait time in ms is only used for the unlock mode. Af-
ter starting the flash unlock, the BDI waits until it pro-
cesses the next entry.

Example:

ERASE 0xff040000 ;erase sector 4 of flash
ERASE 0xff060000 ;erase sector 6 of flash
ERASE 0xff000000 CHIP ;erase whole chip(s)
ERASE 0xff010000 UNLOCK 100 ;unlock, wait 100ms

RECOVER clkd

If this entry is present, the BDI automatically executes a "JTAG lockout re-
covery" during reset processing if the MAC7100 flash is secured. Use this
entry only if you really need to recover a secured a MAC7100 device.

clkd

The value for the CFMCLKD register used during the
JTAG lockout recovery. Calculate this entry based on the
reset system frequency (PLL disabled).

Example:

RECOVER 19 ; CLKD for 8 MHz system clock

Example for the ARM PID7T board (AM29F010 in U12):

[FLASH]

WORKSPACE 0x00000000 ;Workspace in target RAM for faster programming algorithm

CHIPTYPE AM29F ;Flash type

CHIPSIZE 0x20000 ;The size of one flash chip in bytes (e.g. AM29F010 = 0x20000)

BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32)

FILE C:\gdb\pid7t\bootrom.hex ;The file to program

ERASE 0x04000000 ;erase sector 0 of flash SIMM

ERASE 0x04004000 ;erase sector 1 of flash SIMM

ERASE 0x04008000 ;erase sector 2 of flash SIMM

ERASE 0x0400C000 ;erase sector 3 of flash SIMM

ERASE 0x04010000 ;erase sector 4 of flash SIMM

ERASE 0x04014000 ;erase sector 5 of flash SIMM

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Summary of Contents for BDI2000

Page 1: ...bdiGDB JTAG interface for GNU Debugger ARM7 ARM9 User Manual Manual Version 1 17 for BDI2000 1997 2005 by Abatron AG ...

Page 2: ...re 16 2 5 1 Configuration with a Linux Unix host 17 2 5 2 Configuration with a Windows host 19 2 5 3 Recover procedure 20 2 6 Testing the BDI2000 to host connection 21 2 7 TFTP server for Windows NT 21 3 Using bdiGDB 22 3 1 Principle of operation 22 3 2 Configuration File 23 3 2 1 Part INIT 24 3 2 2 Part TARGET 27 3 2 3 Part HOST 31 3 2 4 Part FLASH 32 3 2 5 Part REGS 39 3 3 Debugging with GDB 41 ...

Page 3: ...bdiGDBfor GNU Debugger BDI2000 ARM User Manual 3 Copyright 1997 2005 by ABATRON AG Switzerland V 1 17 7 Appendices A Troubleshooting 53 B Maintenance 54 C Trademarks 56 ...

Page 4: ...pecial debug tasks e g force a hardware reset program flash memory The following figure shows how the BDI2000 interface is connected between the host and the target 1 1 BDI2000 The BDI2000 is the main part of the bdiGDB system This small box implements the interface be tween the JTAG pins of the target CPU and a 10Base T ethernet connector The firmware and the programable logic of the BDI2000 can ...

Page 5: ...T SOFT or HARD HOST IP 151 120 25 100 FILE E cygnus root usr demo arm myapp FORMAT COFF LOAD MANUAL AGENT load application MANUAL or AUTO after reset FLASH WORKSPACE 0x00000000 workspace in target RAM for fast programming algorithm CHIPTYPE AM29F Flash type AM29F AM29BX8 AM29BX16 I28BX8 I28BX16 CHIPSIZE 0x20000 The size of one flash chip in bytes e g AM29F010 0x20000 BUSWIDTH 8 The width of the fl...

Page 6: ...1 13 14 2 1 10 2 The green LED TRGT marked light up when target is powered up Rev A 1 19 20 2 Connector 1 Vcc Target 2 NC 3 TRST 4 NC 5 TDI 6 NC 7 TMS 8 GROUND 9 TCK 10 GROUND 11 NC 12 NC 13 TDO 14 NC 15 RESET 16 NC 17 NC 18 NC 19 NC 20 NC 1 Vcc Target 2 GROUND 3 TRST 4 GROUND 5 TDI 6 NC 7 TMS 8 NC 9 TCK 10 NC 11 TDO 12 RESET 13 NC 14 NC 20 pin Multi ICE Connector BDI2000 A A A Ab b b ba a a at t ...

Page 7: ...This output of the BDI2000 connects to the target TCK line 6 TMS JTAG Test Mode Select This output of the BDI2000 connects to the target TMS line 7 RESET This open collector output of the BDI2000 is used to reset the target system 8 TDI JTAG Test Data In This output of the BDI2000 connects to the target TDI line 9 Vcc Target 1 8 5 0V This is the target reference voltage It indicates that the targe...

Page 8: ...up has to be done see chapter 2 5 During this process the target cable must be disconnected from the target system The BDI2000 needs to be supplied with 5 Volts via the BDI OPTION connec tor Rev A or via the POWER connector Rev B C For more information see chapter 2 2 1 External Power Supply To avoid data line conflicts the BDI2000 must be disconnected from the target system while programming the ...

Page 9: ...or more information about adaptive clocking see ARM documentation Note Adaptive clocking is only supported with BDI2000 Rev B C and a special target cable This special cable can be ordered separately from Abatron For TARGET B connector signals see table on next page BDI2000 A A A Ab b b ba a a at t t tr r r ro o o on n n n A A A AG G G G S S S Sw w w wi i i is s s ss s s s M M M Ma a a ad d d de e...

Page 10: ...s It also controls the output logic levels to the target It is normally fed from Vdd I O on the target board 3 0 5 0V with Rev A B This input to the BDI2000 is used to detect if the target is powered up If there is a current limiting resistor between this pin and the target Vdd it should be 100 Ohm or less 7 TCK JTAG Test Clock This output of the BDI2000 connects to the target TCK line 8 TRST JTAG...

Page 11: ...en 4 75V and 5 25V DC The maximal tolerable supply voltage is 5 25 VDC Any higher voltage or a wrong polarity might destroy the electronics Please switch on the system in the following sequence 1 external power supply 2 target system BDI TRGT MODE BDI MAIN BDI OPTION 13 1 14 2 BDI OPTION 1 NOT USED 2 GROUND 3 NOT USED 4 GROUND 5 NOT USED 6 GROUND 7 NOT USED 8 GROUND 9 NOT USED 10 GROUND 11 NOT USE...

Page 12: ...ation the power supply to the BDI2000 must be between 4 75V and 5 25V DC The maximal tolerable supply voltage is 5 25 VDC Any higher voltage or a wrong polarity might destroy the electronics BDI TRGT MODE BDI MAIN BDI OPTION 13 1 14 2 BDI OPTION Connector The green LEDs BDI and TRGT marked light up when target is powered up Jumper and the jumper is inserted correctly 1 NOT USED 2 GROUND 3 NOT USED...

Page 13: ...D indicates the following BDI states MODE LED BDI STATES OFF The BDI is ready for use the firmware is already loaded ON The power supply for the BDI2000 is 4 75VDC BLINK The BDI loader mode is active an invalid firmware is loaded or loading firmware is active BDI TRGT MODE BDI MAIN BDI OPTION BDI TRGT MODE TARGET A TARGET B Rev A Rev B C ...

Page 14: ...RS232 Connector for PC host 5 2 3 7 8 6 1 4 5 2 3 7 8 6 1 4 GND RD TD RTS CTS DSR DCD DTR GND RD TD RTS CTS DSR DCD DTR BDI2000 A A A Ab b b ba a a at t t tr r r ro o o on n n n A A A AG G G G S S S Sw w w wi i i is s s ss s s s M M M Ma a a ad d d de e e e Target System RS232 ARM 7TDMI RS232 LI TX RX 10 BASE T 5 4 3 2 1 9 8 7 6 PC Host Rev A RS232 Connector for PC host 5 2 3 7 8 6 1 4 5 2 3 7 8 6...

Page 15: ...eanings of the built in LED lights LED Name Description LI Link When this LED light is ON data link is successful between the UTP port of the BDI2000 and the hub to which it is connected TX Transmit When this LED light BLINKS data is being transmitted through the UTP port of the BDI2000 RX Receive When this LED light BLINKS data is being received through the UTP port of the BDI2000 10 BASE T PC Ho...

Page 16: ... the entire contents of the enclosed diskette into this directory Linux only extract the setup tool sources and build the setup tool Use the setup tool to load update the BDI firmware logic Note A new BDI has no firmware logic loaded Use the setup tool to transmit the initial configuration parameters IP address of the BDI IP address of the host with the configuration file Name of the configuration...

Page 17: ...c cc O2 c o bdicnf o bdicnf c cc O2 c o bdidll o bdidll c cc s bdisetup o bdicnf o bdidll o o bdisetup 2 Check the serial connection to the BDI With bdisetup v you may check the serial connection to the BDI The BDI will respond with infor mation about the current loaded firmware and network configuration Note Login as root otherwise you probably have no access to the serial port root LINUX_1 bdise...

Page 18: ...very start up Configuration file Enter the full path and name of the configuration file This file is read via TFTP Keep in mind that TFTP has it s own root directory usual tftpboot You can simply copy the configuration file to this directory and the use the file name without any path For more information about TFTP use man tftpd root LINUX_1 bdisetup bdisetup c p dev ttyS0 b57 i151 120 25 101 h151...

Page 19: ...this Channel Select the communication port where the BDI2000 is connected during this setup session Baudrate Select the baudrate used to communicate with the BDI2000 loader during this setup session Connect Click on this button to establish a connection with the BDI2000 loader Once connected the BDI2000 remains in loader mode until it is restarted or this dialog box is closed Current Press this bu...

Page 20: ...very start up Configuration file Enter the full path and name of the configuration file e g D ada target config bdi evs332 cnf For information about the syntax of the configuration file see the bdiGDB User manual This name is transmitted to the TFTP server when reading the configuration file Transmit Click on this button to store the configuration in the BDI2000 flash memory 2 5 3 Recover procedur...

Page 21: ...ides a TFTP server appli cation tftpsrv exe This WIN32 console application runs as normal user application not as a system service Command line syntax tftpsrv p w dRootDirectory Without any parameter the server starts in read only mode This means only read access request from the client are granted This is the normal working mode The bdiGDB system needs only read access to the configuration and pr...

Page 22: ... There is no need for any debug software on the target system After loading the code via TFTP debugging can begin at the very first assembler statement Whenever the BDI system is powered up the following sequence starts Power On initial configuration valid Get configuration file via TFTP Process target init list via TFTP and set the PC Load program code Process GDB request Power OFF activate BDI20...

Page 23: ...eakpoints All the time the application is suspended i e caused by a breakpoint the target processor remains in debug mode 3 2 Configuration File The configuration file is automatically read by the BDI2000 after every power on The syntax of this file is as follows comment part name core identifier parameter1 parameter2 parameterN comment core identifier parameter1 parameter2 parameterN part name co...

Page 24: ...e chapter CP15 registers value the value to write into the register Example WCP15 2 0x00004000 set Translation Base Address WM8 address value Write a byte 8bit to the selected memory place address the memory address value the value to write to the target memory Example WM8 0xFFFFFA21 0x04 SYPCR watchdog disable WM16 address value Write a half word 16bit to the selected memory place address the mem...

Page 25: ...mory place address the memory address Example RM32 0x00000000 MMAP start end Because a memory access to an invalid memory space via JTAG leads to a deadlock this entry can be used to define up to 32 valid memory ranges If at least one memory range is defined the BDI checks against this range s and avoids accessing of not mapped memory ranges start the start address of a valid memory range end the ...

Page 26: ... Example FILE F gdb target config pid7t startup hex FORMAT format The format of the startup file Currently COFF S Record a out Binary and ELF file formats are supported If the startup code is already stored in ROM on the target select ROM as the format format COFF SREC AOUT BIN ELF or ROM Example FORMAT COFF START address The address where to start the startup code If this value is not defined and...

Page 27: ...d needs a special target connector cable main init 0 Adaptive 1 16 MHz 6 200 kHz 2 8 MHz 7 100 kHz 3 4 MHz 8 50 kHz 4 1 MHz 9 20 kHz 5 500 kHz 10 10 kHz Example CLOCK 1 JTAG clock is 16 MHz RESET type time Normally the BDI drives the reset line during startup If reset type is NONE the BDI does not assert a hardware reset during startup This entry can also be used to change the default reset time t...

Page 28: ... 3sec wake up time BDIMODE mode param This parameter selects the BDI debugging mode The following modes are supported LOADONLY Loads and starts the application code No debugging via JTAG interface AGENT The debug agent runs within the BDI There is no need for any debug software on the target This mode accepts a second parameter If RUN is entered as a second pa rameter the loaded application will b...

Page 29: ...kpoints Example BREAKMODE HARD BREAKMODE SOFT 0xdfffdfff STEPMODE mode This parameter defines how single step instruction step is implemented The alternate step mode HWBP may be useful when stepping instruc tions should not enter exception handling JTAG This is the default mode For ARM9 targets the JTAG single step feature is used For ARM7 targets a range breakpoint that excludes the current instr...

Page 30: ...se the normal Telnet connection to the BDI in parallel they work completely independent Also input to DCC is implemented port The TCP IP port used for the host communication Example DCC 7 TCP port for DCC I O Daisy chained JTAG devices For ARM targets the BDI can also handle systems with multiple devices connected to the JTAG scan chain In order to put the other devices into BYPASS mode and to cou...

Page 31: ...s defines if the code is loaded automatically after every reset mode AUTO MANUAL Example LOAD MANUAL START address The address where to start the program file If this value is not defined and the core is not in ROM the address is taken from the code file If this value is not defined and the core is already in ROM the PC will not be set before starting the target This means the program starts at th...

Page 32: ...ps Do not en ter the width of the flash chip itself The parameter CHIPTYPE carries the information about the number of data lines connected to one flash chip For example enter 16 if you are using two AM29F010 to build a 16bit flash memory bank with the width of the flash memory bus in bits 8 16 32 Example BUSWIDTH 16 FILE filename The default name of the file that is programmed into flash using th...

Page 33: ...SE 0xff040000 erase sector 4 of flash ERASE 0xff060000 erase sector 6 of flash ERASE 0xff000000 CHIP erase whole chip s ERASE 0xff010000 UNLOCK 100 unlock wait 100ms RECOVER clkd If this entry is present the BDI automatically executes a JTAG lockout re covery during reset processing if the MAC7100 flash is secured Use this entry only if you really need to recover a secured a MAC7100 device clkd Th...

Page 34: ...stem Clock Frequency CCLK in KHz This frequency has to be provided via the CHIPTYPE parameter CHIPTYPE LPC2000 fsys kHz CHIPTYPE LPC2000 14745 select LPC2100 flash fsys 14 745MHz The erase parameter has a different meaning It is not an address but a bit map of the sectors to erase bit0 erase sector 0 bit1 erase If you add BLANK after the sector map then a blank check is executed after the erase Fo...

Page 35: ... 32 select 32 for this flash FILE sta2051b0 bin The file to program FORMAT BIN 0x40000000 ERASE 0x000000FF erase all sectors of bank 0 ST30F7xx Internal Flash The ST30F7xx flash is handled like the STA2051 flash The only difference is that there exists only flash bank 0 but with 12 sectors ERASE 0x00000FFF erase all sectors of bank 0 ADuC7000 Internal Flash The BDI2000 supports programming of the ...

Page 36: ...KR MCK PLL 2 48MHz DELAY 20 Setup Internal Flash for 48MHz Master Clock WM32 0xFFFFFF60 0x00300100 MC_FMR Flash mode FWS 1 FMCN 48 TARGET CPUTYPE ARM7TDMI CLOCK 1 10 JTAG clock start with a slow clock RESET HARD 300 Assert reset line for 300 ms BREAKMODE HARD SOFT or HARD STEPMODE HWBP FLASH CHIPTYPE AT91SAM7S Don t forget to set MC_FMR FMCN and MC_FMR FWS CHIPSIZE 0x10000 The AT91SAM7S64 has 64kB...

Page 37: ...AT49 algorithm support chip erase Block erase is only supported with the AT49 algorithm If the algorithm does not support the selected mode sector erase is performed If the chip does not support the selected mode erasing will fail The erase command sequence is different only in the 6th write cycle Depending on the selected mode the following data is written in this cycle see also flash data sheets...

Page 38: ...ts of an Intel J3 Strata flash takes up to 0 7 seconds If unlock is used without any parameter all sectors in the erase list with the UNLOCK option are processed To clear all lock bits of an Intel J3 Strata flash use for example BDI unlock 0xFF000000 1000 To erase or unlock multiple continuos flash sectors blocks of the same size the following Telnet commands can be used ERASE addr step count UNLO...

Page 39: ...12 characters type The register type GPR General purpose register CP15 Coprocessor 15 register MM Absolute direct memory mapped register DMM1 DMM4 Relative direct memory mapped register IMM1 IMM4 Indirect memory mapped register addr The address offset or number of the register size The size 8 16 32 of the register The following entries are supported in the REGS part of the configuration file FILE ...

Page 40: ...E0000432 csr2 MM 0xFFE0000832 csr3 MM 0xFFE0000c32 csr4 MM 0xFFE0001032 csr5 MM 0xFFE0001432 csr6 MM 0xFFE0001832 csr7 MM 0xFFE0001c32 rcr MM 0xFFE0002032 mcr MM 0xFFE0002432 Now the defined registers can be accessed by name via the Telnet interface BDI rd csr0 BDI rm csr0 0x01002535 Example for CP15 register definition ARM720T id CP15 0x0000 32 control CP15 0x0001 32 ttb CP15 0x0002 32 dac CP15 0...

Page 41: ...diately started otherwise only the target PC is set BDI now waits for GDB request from the debugger running on the host After starting the debugger it must be connected to the remote target This can be done with the fol lowing command at the GDB prompt gdb target remote bdi2000 2001 bdi2000 This stands for an IP address The HOST file must have an appropriate entry You may also use an IP address in...

Page 42: ...you should se lect BREAKMODE HARD and disable vector catching For ARM9E the BKPT instruction is always used to implement software breakpoints In that case no hardware breakpoint watchpoint is used to implement software breakpoints User controlled hardware breakpoints The ARM IceBreaker has a special watchpoint hardware integrated Normally the BDI controls this hardware in response to Telnet comman...

Page 43: ...r SIO is used to enable this serial I O routing The BDI asserts RTS and DTR when a TCP connection is established TARGET SIO 7 9600 Enable SIO via TCP port 7 at 9600 baud Warning Once SIO is enabled connecting with the setup tool to update the firmware will fail In this case either disable SIO first or disconnect the BDI from the LAN while updating the firmware Target System Ethernet 10 BASE T BDI2...

Page 44: ...e versa Below some simple functions you can link to your application in order to implement IO via DCC define DCC_OUTPUT_BUSY 2 define DCC_INPUT_READY 1 static unsigned int read_dcc void unsigned int c __asm__ mrc p14 0 0 c1 c0 n r c return c static void write_dcc unsigned int c __asm__ mcr p14 0 0 c1 c0 n r c static unsigned int poll_dcc void unsigned int ret __asm__ mrc p14 0 0 c0 c0 n r ret retu...

Page 45: ...isters Single step a code sequence Set hardware breakpoints for code and data accesses Load a code file from any host Start Stop program execution Programming and Erasing Flash memory During debugging with GDB the Telnet is mainly used to reboot the target generate a hardware reset and reload the application code It may be also useful during the first installation of the bdiGDB sys tem or in case ...

Page 46: ...n HALT n n n n force core s to debug mode n core number BI addr mask set instruction breakpoint CI id clear instruction breakpoint s BD R W addr data set data watchpoint 32bit access BDH R W addr data set data watchpoint 16bit access BDB R W addr data set data watchpoint 8bit access BDM R W addr mask set data watchpoint with address mask CD id clear data watchpoint s INFO display information about...

Page 47: ...d therefore you can simply enter the CP15 register number In the register definition file reg720t def you will find some examples ARM920T Via JTAG CP15 registers are accessed either direct physical access mode or via interpreted MCR MRC instructions Read also ARM920T manual part Debug Support Scan Chain 15 Register number for physical access mode bit 12 0 0 0 0 0 0 0 0 i 0 0 0 x nbr The bit i sele...

Page 48: ...functions 0 or 0x30 ID 1 or 0x31 Control 2 or 0x32 Translation table base 3 or 0x33 Domain access control 5 or 0x35 Fault status 6 or 0x36 Fault address 8 or 0x38 Cache information 13 or 0x3d Process ID 0x10 TI925T Status 0x11 TI925T Configuration 0x12 TI925T I max 0x13 TI925T I min 0x14 TI925T Thread ID 0x18 Flush I D TLB 0x19 Flush I TLB 0x1a Flush I TLB entry 0x1b Flush D TLB 0x1c Flush D TLB e...

Page 49: ... on the scan chain TARGET CLOCK 1 JTAG clock 0 Adaptive 1 8MHz 2 4MHz 3 2MHz WAKEUP 1000 wakeup time after reset 0 CPUTYPE ARM7TDMI 0 SCANPRED 0 0 JTAG devices connected before this core 0 SCANSUCC 1 4 JTAG devices connected after this core 0 VECTOR CATCH catch unhandled exceptions 0 BREAKMODE SOFT 0xef180000 SOFT or HARD X Tools V1 0 break code 0 DCC 8 DCC I O via TCP port 8 1 CPUTYPE ARM7TDMI 1 ...

Page 50: ... 200 38 400 57 600 115 200 Data Bits 8 Parity Bits none Stop Bits 1 Network Interface 10 BASE T Serial Transfer Rate between BDI and Target up to 16 Mbit s Supported target voltage 1 8 5 0 V 3 0 5 0 V with Rev A B Operating Temperature 5 C 60 C Storage Temperature 20 C 65 C Relative Humidity noncondensing 90 rF Size 190 x 110 x 35 mm Weight without cables 420 g Host Cable length RS232 2 5 m Specif...

Page 51: ...ebugger BDI2000 ARM User Manual 51 Copyright 1997 2005 by ABATRON AG Switzerland V 1 17 5 Environmental notice Disposal of the equipment must be carried out at a designated disposal site 6 Declaration of Conformity CE ...

Page 52: ... but not limited loss of profit special incidental consequential or other similar claims ABATRON Switzerland specifically disclaims all other warranties expressed or implied including but not limited to implied warranties of merchantability and fitness for particular purposes with respect to defects in the diskette cable BDI2000 and documentation and the program license granted here in including w...

Page 53: ...ication port Com 1 Com 4 is selected Problem No working with the target system loading firmware is ok Possible reasons Wrong pin assignment BDM JTAG connector of the target system see chapter 2 Target system initialization is not correctly enter an appropriate target initialization list An incorrect IP address was entered BDI2000 configuration BDM JTAG signals from the target system are not correc...

Page 54: ...please proceed according to the following steps Observe precautions for handling Electrostatic sensitive device Unplug the cables before opening the cover Use exact fuse replacement Microfuse MSF 1 6 AF 1 2 3 BDI 2000 A A A A b b b b a a a a t t t t r r r r o o o o n n n n A A A A G G G G S S S S w w w w i i i i s s s s s s s s M M M M a a a a d d d d e e e e 1 1 Unplug the cables BDI TRGT MODE BD...

Page 55: ...lign with the holes in the front panel elastic sealing Reinstallation back panel 5 2 Push carefully the front panel and the red elastig sealing on the casing Check that the LEDs align with the holes in the front panel and that the 5 3 Mount the screws do not overtighten it 5 4 Mount the two plastic caps that cover the screws 5 5 Plug the cables position of the sealing is as shown in the figure bel...

Page 56: ...bdiGDBfor GNU Debugger BDI2000 ARM User Manual 56 Copyright 1997 2005 by ABATRON AG Switzerland V 1 17 C Trademarks All trademarks are property of their respective holders ...

Page 57: ...ommunication via RS232 and Ethernet Program download speed up to 320 Kbytes s Target communication speed up to 16 Mbits s Supports target system voltage from 1 8 5V Support debuggers from leading vendors Same hardware for all supported targets and debuggers Flash memory on board programming Easy connection to target system Robust EMC optimized design Excellent price performance payoff 3 year hardw...

Page 58: ...ages eliminate the need for expensive hardware such as an in circuit emulator Even better the BDI2000 accesses the on chip emulation capabilities of today s newest processors which aren t supported by traditional ICEs Advanced Hardware Technology As a result of consistent implementation of latest technology the BDI2000 is optimally prepared for further enhancements The firmware and the programmabl...

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