bdi
GDB
for GNU Debugger, BDI2000 (ARM)
User Manual
48
© Copyright 1997-2005 by ABATRON AG Switzerland
V 1.17
ARM926E:
The 16bit register number contains the fields of the appropriate MCR/MRC instruction that would be
used to access the CP15 register.
+-+-----+-+-----+-------+-------+
|-|opc_1|-|opc_2| CRm | nbr |
+-+-----+-+-----+-------+-------+
Normally opc_1, opc_2 and CRm are zero and therefore you can simply enter the CP15 register num-
ber. In the register definition file "reg926e.def" you will find some examples.
TI925T:
The CP15 registers are directly accessed via JTAG.
The following table shows the numbers used to access the CP15 registers and functions.
0 (or 0x30) : ID
1 (or 0x31) : Control
2 (or 0x32) : Translation table base
3 (or 0x33) : Domain access control
5 (or 0x35) : Fault status
6 (or 0x36) : Fault address
8 (or 0x38) : Cache information
13 (or 0x3d) : Process ID
0x10 : TI925T Status
0x11 : TI925T Configuration
0x12 : TI925T I-max
0x13 : TI925T I-min
0x14 : TI925T Thread ID
0x18 : Flush I+D TLB
0x19 : Flush I TLB
0x1a : Flush I TLB entry
0x1b : Flush D TLB
0x1c : Flush D TLB entry
0x20 : Flush I cache
0x22 : Flush I cache entry
0x23 : Flush D cache
0x24 : Flush D cache entry address
0x25 : Clean D cache entry address
0x26 : Clean + Flush D cache entry address
0x27 : Flush D cache entry index
0x28 : Clean D cache entry index
0x29 : Clean + Flush D cache entry index
0x2a : Clean D cache
0x2b : Drain Write buffer
0x37 : I cache TLB Lock-Down
0x3a : D cache TLB Lock-Down
