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Summary of Contents for XVR16 Series

Page 1: ...Generation Intel Core i7 Based Rugged VME S ingle Board Computer THE XVR16 IS DESIGNED TO MEET THE EUROPEAN UNION EU RESTRICTIONS OF HAZARDOUS SUBSTANCE ROHS DIRECTIVE 2002 95 EC CURRENT REVISION Publication No 500 9300007876 000 Rev C 0 ...

Page 2: ...nnector built options Partial Limited and Full In Section 1 1 6 Table A 11 correct the DMS59 Connector Digital Pin Assignments DVI1 and DVI2 C 0 September 2016 Reformatting Abaco Systems is registered with an approved Producer Compliance Scheme PCS and subject to suitable contractual arrangements being in place will ensure WEEE is processed in accordance with the requirements of the WEEE Directive...

Page 3: ... numbers have a b subscript The prefix 0x shows a hexadecimal number following the C programming language convention Thus One dozen 12D 0x0C 1100b The multipliers k M and G have their conventional scientific and engineering meanings of x103 x106 and x109 respectively The only exception to this is in the description of the size of memory areas when k M and G mean x210 x220 and x230 respectively NOT...

Page 4: ... National Standard for VME64 R2002 ANSI VITA 1 1 1997 American National Standards for VME64 Extensions R2003 ANSI VITA 20 2001 American National Standard for Conduction Cooled PMC ANSI TIA EIA 485 A March 1998 ANSI TIA EIA 422 B January 2000 ANSI VITA 31 1 2003 VMEbus International Trade Association ANSI VITA 32 2003 PMC Standard for Processor PCI Mezzanine Cards R2009 ANSI VITA 35 2000 American N...

Page 5: ... and Boundary Scan Architecture June 1993 IEEE 1386 2001 IEEE Standard for a Common Mezzanine Card CMC Family June 2001 IEEE 1386 1 2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC October 2001 IPC IPC A 600 Acceptability of Printed Board Rev F November 1999 IPC IPC A 610 Acceptability of Electronic Assemblies Rev C January 2000 IPC IPC CC 830B Qualification and Per...

Page 6: ...sion 1 0A January 2003 Universal Serial Bus 3 0 Specification Revision 1 0 November 2008 Intel Documents Intel Haswell Mobile Processor External Design Specification EDS Volume 1 of 2 Document No 487246 1 0v1 May 2012 Intel Shark Bay Mobile Platform Design Guide For use with Haswell Mobile rPGA 7 BGA Processor And Lynx Point Platform Controller Hub Pch Revision 1 5 Document Number 486713 September...

Page 7: ...struction Set Reference A M Intel 64 and IA 32 Architectures Software Developerʹs Manual Volume 2B Instruction Set Reference N Z Intel 64 and IA 32 Architectures Software Developerʹs Manual Volume 3A System Programming Guide Part 1 Intel 64 and IA 32 Architectures Software Developerʹs Manual Volume 3B System Programming Guide Part 2 Intel 64 Architecture x2APIC Specification Intel 64 and IA 32 Arc...

Page 8: ... page LINK http www abaco com embedded support Do not return products without first contacting the Abaco Repairs facility Additional Notes This document provides technical information for Abaco Systems XVR16 a rugged single slot VME Single Board Computer SBC in 6U VME form factor equipped with the quad core 4th Generation Intel Core i7 Haswell processor and the Mobile Intel QM87 Chipset Because th...

Page 9: ... power outlet Do Not Operate in an Explosive Atmosphere Do not operate the system in the presence of flammable gases or fumes Operation of any electrical system in such an environment constitutes a definite safety hazard Keep Away from Live Circuits Operating personnel must not remove product covers Component replacement and internal adjustments must be made by qualified maintenance personnel Do n...

Page 10: ...Installation Preparation 28 3 1 1 VMEbus Products 28 3 1 2 Replacing Disposing of Batteries 28 3 2 Required Items 29 3 2 1 Backplane and Power Supply 29 3 2 2 Keyboard and Mouse 29 3 2 3 Video Monitor 29 3 2 4 Minimum System Requirements 29 3 2 5 POST 30 3 3 Installing XVR16 into Chassis 31 3 4 Installation of the Rear Transition Module VTM26 or VTM28 31 3 5 Initial Power On Operation 32 3 6 Enter...

Page 11: ...gies 64 6 1 3 Processor to PCH 64 6 2 QM87 Express Chipset 65 6 3 CPU Memory Controller 65 6 3 1 Memory Controller Features 65 6 4 Graphics Controller 66 6 5 PCI Express Interfaces 67 6 6 Mezzanine PMC XMC Interface 68 6 7 VME Interface 68 6 7 1 VMEbus Features 68 6 7 2 PCI X to VME Bridge Tsi148 Software Guidelines 69 6 7 3 VME SYSRESET Direction 70 6 8 Interrupt Controller 70 6 9 Timer 8254 70 6...

Page 12: ...A Connectors 121 A 1 6 Digital Video Connector DVI 1 2 P4000 122 A 1 7 GPIO Connector P2002 123 A 1 8 Miscellaneous Connector P2000 124 A 1 9 Audio Pinouts 124 A 1 10 PMC I O Connectors 125 A 1 11 Write Protection J2000 126 A 1 12 LED 126 A 2 VTM28 Transition Module 126 A 2 1 VGA1 Interface J31 128 A 2 2 Serial Interfaces COM1 J100 and COM2 P10 128 A 2 3 Ethernet Interface 10 100 1000BASE T J29 J3...

Page 13: ...9300007876 000 Rev C 0 Table of Contents 13 D Processor Speed and Temperature 149 D 1 Quad Core i7 4700EQ 47 W 2 4 GHz Processor Option 149 E Statement of Volatility 150 E 1 Volatile Memory 150 E 2 Non Volatile Memory 150 ...

Page 14: ...in Assignments J21 49 Figure 5 15 PMC2 Connector Pin Assignments J22 50 Figure 5 16 PMC2 Connector Pin Assignments J23 51 Figure 5 17 PMC2 Connector Pin Assignments J24 52 Figure 5 18 XMC Connector J15 and J16 54 Figure 5 19 XMC Connector J25 56 Figure 5 20 XMC Connector J26 57 Figure 6 1 Block Diagram 63 Figure 6 2 PCI Express Channels 67 Figure 6 3 Power Button 77 Figure 8 1 Block Diagram for FP...

Page 15: ...No 500 9300007876 000 Rev C 0 List of Figures 15 Figure C 1 Mounting PMC XMC Module onto XVR16 146 Figure C 2 Mounting of Secondary Thermal Interface on PMC Module 147 Figure C 3 Installing HD ADAP8 SATA Module 148 ...

Page 16: ...5 56 Table 5 19 XMC2 I O Connector Pin Assignments J26 57 Table 5 20 VMEbus Connector P0 with Full PMC I O Ordering Option G 1 or 4 58 Table 5 21 VMEbus Connector P0 with Limited PMC I O Ordering Option G 0 or 3 59 Table 5 22 VMEbus Connector P0 with Partial PMC I O Ordering Option G 2 or 5 60 Table 5 23 VMEbus Connector P1 61 Table 5 24 VMEbus Connector P2 62 Table 6 1 Interval Timer Functions 71...

Page 17: ... 0x676 95 Table 8 37 GPIO 7 0 Interrupt Status Register 0x677 95 Table 8 38 GPIO 7 0 Availability Register 0x678 96 Table 8 39 GPIO 15 8 OUT Register 0x67C 96 Table 8 40 GPIO 15 8 IN Register 0x67D 96 Table 8 41 GPIO 15 8 Direction Register 0x67E 97 Table 8 42 GPIO 15 8 Interrupt Enable Register 0x67F 97 Table 8 43 GPIO 15 8 Interrupt Level Edge Register 0x680 97 Table 8 44 GPIO 15 8 Interrupt Hig...

Page 18: ...rmal Status Register 0x6D0 108 Table 8 81 Thermal Alarm Status Register 0x6D1 108 Table 9 1 Levels Available 109 Table 9 2 CPU Power Consumption 110 Table 9 3 Battery Lifetime 111 Table 9 4 5VSTDBY Current Consumption 113 Table 9 5 Environmental Conditions 113 Table 9 6 Maximum Altitude Usage 114 Table 9 7 Supply Voltages 114 Table 9 8 Supply Voltage Range 114 Table 9 9 GPIO IN Signal Levels 115 T...

Page 19: ...ITFail Status LED 135 Table A 28 Rear Status LED 135 Table B 1 BIOS Firmware First Boot Menu 136 Table B 2 BIOS Main Menu 137 Table B 3 BIOS Advanced Menu 138 Table B 4 BIOS Chipset Menu 140 Table B 5 Server Mgmt Menu 141 Table B 6 BIOS Boot Menu 142 Table B 7 BIOS Security Menu 143 Table B 8 BIOS Save Exit Menu 144 Table C 1 Electrical Characteristics 145 Table D 1 Maximum Operating Frequency ver...

Page 20: ...C up to 16 GByte Up to 6 MByte shared cache Up to 64 GByte NAND Flash Front I O 2x Gigabit Ethernet ports second port is optionally available 1x DisplayPort 2x USB ports second port is USB 3 0 and optional 1x COM port 1x Power button 1 x eSATA optional Rear I O via Transition Module Actual I O depends on option ordered 2x Gigabit Ethernet ports VITA 31 1 2x Video Graphics Array VGA 2x Digital Vide...

Page 21: ...perating systems and also require software driver and Board Support Packages BSPs to support the low level hardware functions 1 2 1 Device Driver Support The XVR16 is shipped with a CD containing standard Windows Device Drivers for Chipset Video and Networking These drivers have been tested with the product and are made available for general customer use See the ʺReadme TXTʺ file on the CD for det...

Page 22: ...ower Requirements 5 3 3 V 12 V mezzanine only Mechanical 6U 1 slot 4 HP conduction cooled IEEE 1101 2 1992 compliant Shock and Vibration Stiffener bars and wedge locks are available depending on board level See Chapter 9 Specifications on page 109 for further details on the physical environmental attributes of the XVR16 ...

Page 23: ...wn as Electrostatic Discharge or ESD is a major cause of electronic component failure The XVR16 has been packed in a static safe bag which protects the board from ESD while the board is in the bag Before removing the XVR16 or any other electronic product from its static safe bag be prepared to handle it in a static safe environment A properly functioning antistatic strap should be worn and the han...

Page 24: ...e measures NOTE Drain static electricity before you install or remove any parts Installing or removing modules without observing this precaution could result in damage to this and or other modules in your system 2 2 2 Unpacking the Board Please read the Manual carefully before unpacking the board or module or installing the device into your system Also adhere to the following 1 Observe all precaut...

Page 25: ...Publication No 500 9300007876 000 Rev C 0 Unpacking and Handling 25 Figure 2 1 Board Packaging Retain all packing material in case of future need ...

Page 26: ...hown Do not handle the board by the circuit card edges the heat sink or the connectors Figure 2 2 Handling the Board CAUTION Handle the board by the edges or front panel only 2 3 1 Handling the Board 1 Ensure that both the person handling the board and the surrounding area are protected from ESD 2 Carefully remove the board or module from the shipping carton by grasping it by the front panel and t...

Page 27: ...atsink could lead to performance degradation or permanent damage Always use the handles provided on the Front Panel 2 3 3 Installation and Power Up Reset A reset button is located at the front and rear Please review the Safety Summary on page 9 before installing the XVR16 CAUTION Ensure that the XVR16 s power requirements are compatible with those supplied by the backplane The XVR16 power requirem...

Page 28: ...tted into the system and all connections have been made properly 3 1 1 VMEbus Products On a standard VMEbus backplane remove the jumpers on the IACKIN IACKOUT interrupt daisy chain 1 jumper and on the BGxIN BGxOUT bus grant daisy chains 4 jumpers for the slot where the board is to be mounted The daisy chain jumpers on the VMEbus backplane should be mounted on all free slots Setting jumpers is not ...

Page 29: ...Mouse A compatible keyboard for initial system operation is required Depending on the application this keyboard may be a standard keyboard or one which utilizes membrane switches for harsh environments The keyboard is attached via a USB connector 3 2 3 Video Monitor The XVR16 offers front panel access to the video signal through the DP DisplayPort Video is also available via the P2 P0 VME connecto...

Page 30: ...are checksum must be valid meaning that it must be readable CMOS RAM is readable CPU must be able to read all forms of memory such as the memory controller memory bus and memory module The first 1 MByte of memory must be operational and have the capability to be read and written to and from and capable of containing the POST code I O bus controller must be accessible If the computer passes all POS...

Page 31: ...VTM28 is a 6U x 80 mm rear I O module which plugs into the XVR16 separated by the backplane These transition modules have a DVI or VGA connector which can be used for monitor connection Plug the monitor into this connector Make sure that the selected chassis supports this type of rear I O transition module After ensuring that the XVR16 is properly installed into the VME backplane apply power to th...

Page 32: ...ering the UEFI Firmware SETUP To enter SETUP during the initial power on sequence Press the DELETE key during the boot up sequence Also see the applicable on screen messages when prompted See Appendix B BIOS Setup Utility LINK Consult the User s Manual www ami com for AMI UEFI Firmware Setup for further information on how to change settings and configurations If the board does not perform as descr...

Page 33: ...ng the voltages at the used power connectors can result in wrong values which are caused by the high current flowing The 5 V and 3 3 V should reach their nominal value when measuring with a multimeter If the voltages are less than 5 0 V or 3 3 V when the CPU or memory perform intensively the voltage may drop causing the XVR16 to reset 4 2 Setup To enter the UEFI Firmware Setup press the keyboard D...

Page 34: ...Setup Utility NOTE The BIOS referred to in this Manual is an EFI BIOS CAUTION Battery backup of critical CMOS settings is provided by the system via the VBAT signal on the VME backplane If the board is removed from the backplane these settings will be lost if no battery is installed onboard 4 3 Unexpected Resets A set of special registers is implemented onboard to locate the reset source in the ev...

Page 35: ...10 S1 P3 P6 P4 XBT1 U191 U190 U174 U173 J34 J32 J15 J11 J16 J12 J13 J14 J21 PMC1 PMC2 PMC1 J23 J24 J22 PMC2 PMC2 PMC2 J25 J26 XMC2 XMC2 XMC1 P4 CMOS Clear Jumper P6 Onboard Hardware Write Protect Jumper ETH3 P1 P2 P0 64 63 1 1 63 2 64 64 63 1 1 2 63 64 64 1 2 63 63 63 63 2 2 2 64 1 1 1 2 2 64 64 F1 E1 D1 C1 B1 A1 F19 E19 D19 C19 B19 A19 U35 U31 U30 U29 U34 U36 U37 U32 U25 U33 U20 U21 U27 U26 U24 U...

Page 36: ...rial link interface Ethernet Activity L Blinks green when the Ethernet is linked and active It remains steady if the Ethernet is linked with no activity Ethernet Speed S Indicates at which speed the Ethernet is running 10BASE T LED is off 100BASE TX Green LED 1000BASE T Amber LED DP DisplayPort Two lane DisplayPort to VGA adapter 3 6 PMC1 XMC1 PMC2 XMC2 USB 2 0 COM3 LAN DP Single PMC FP Option Dua...

Page 37: ...the four graphic ports available on the XVR16 The front panel DisplayPort is a single horizontal 20 pin connector that connects to an adapter cable For further information on the other video display types that are routed out the backplane see Section 6 4 Graphics Controller Figure 5 3 DisplayPort Front Panel Connector J31 Table 5 1 DisplayPort J31 Pin Signal Pin Signal 1 DPB_LANE0_P 11 GND 2 GND 1...

Page 38: ... the XMC PMC site 2 is not chosen as an option Two GbE channels ETH3 and ETH4 are routed out the backplane to P0 and are always available Figure 5 4 Ethernet RJ45 Interface Table 5 2 LAN Standard GbE J27 or Optional LAN J34 Two LEDs LED1 green and LED2 yellow are integrated in each of the RJ45 connectors These LEDs indicate the link status of the interface LAN 10 100BASE T 1000BASE T 1 TxD MDI0 2 ...

Page 39: ... har Link adapter cable is available to convert the 10 pin har Link connector to a standard Sub D9 connector Part No YLB CR12 01 Figure 5 5 COM3 Location Table 5 4 Serial Port COM3 Connector J28 har Link Connector RS232 DSUB Male Connector A1 RXD 2 B1 TXD 3 C1 RS232 driver disablea N A D1 DTR 4 E1 DSR 6 A2 RTS 7 B2 RI 9 C2 GND 5 D2 CTS 8 E2 DCD 1 a A low on this signal disables this port E2 E1 A1 ...

Page 40: ... 0 Interface J29 USB 2 0 is available at the front panel Two USB 2 0 ports are available on the rear I O at P2 Figure 5 6 USB 2 0 Port Figure 5 7 USB Pin Locations Table 5 5 USB 2 0 Connector Front Panel J29 Pin Name 1 VCCa 2 USB 3 USB 4 GND a This pin is currently limited at 1 5A For normal operation do not exceed 1A current 1 4 ...

Page 41: ...s provided for USB 3 0 high speed differential signals The USB 3 0 connector is available only when the XMC PMC site 2 is not chosen as an option Figure 5 8 USB 3 0 Interface Table 5 6 USB 3 0 Connector Front Panel J30 NOTE a This pin is currently limited at 1 5A For normal operation do not exceed 1A current 5 2 6 LAN Optional J34 See Section 5 2 2 Ethernet Interface RJ45 Pin Name 1 VCCa 2 USB 3 U...

Page 42: ... Connectors J11 J12 J13 J14 The following tables list the pin assignments of the onboard PMC1 connectors J11 J12 J13 J14 The PMC1 slot is 64 bit up to PCI X 133 MHz capable and works with a PCIe PCI bridge Pericom PI7C9X130 The PCI bridge and PMC1 bus are disabled when a PMC card is not installed or an XMC card is installed at this slot PMC disabling can be overruled by UEFI Firmware Setup adjustm...

Page 43: ...Publication No 500 9300007876 000 Rev C 0 Connectors 43 Legend for PMC Tables Active Low Signal NC Not Connected Reserved Do not connect anything V I O I O Voltage connected with 3 3 V ...

Page 44: ...06 PMC1INTC PRESENT 07 08 5 V PMC1INTD 09 10 Reserved GND 11 12 PCI RSVD 3V3 PCICLK 13 14 GND GND 15 16 GNT0 REQ0 17 18 5 V V I O 19 20 AD31 AD28 21 22 AD27 AD25 23 24 GND GND 25 26 CBE3 AD22 27 28 AD21 AD19 29 30 5 V V I O 31 32 AD17 FRAME 33 34 GND GND 35 36 IRDY DEVSEL 37 38 5 V PCIXCAP 39 40 LOCK SDONE 41 42 SB0 PAR 43 44 GND V I O 45 46 AD15 AD12 47 48 AD11 AD9 49 50 5 V GND 51 52 CBE0 AD6 53...

Page 45: ...3 V 15 16 PDN 2a PME 17 18 GND AD30 19 20 AD29 GND 21 22 AD26 AD24 23 24 3 3 V IDSEL 25 26 AD23 3 3 V 27 28 AD20 AD18 29 30 GND AD16 31 32 CBE2 GND 33 34 IDSELB TRDY 35 36 3 3 V GND 37 38 STOP PERR 39 40 GND 3 3 V 41 42 SERR CBE1 43 44 GND AD14 45 46 AD13 M66EN 47 48 AD10 AD8 49 50 3 3 V AD7 51 52 REQB 3 3 V 53 54 GNTB Reserved 55 56 GND Reserved 57 58 Reserved ERDY GND 59 60 Reserved RSTOUT ACK64...

Page 46: ... 06 CBE5 CBE4 07 08 GND V I O 09 10 PAR64 AD63 11 12 AD62 AD61 13 14 GND GND 15 16 AD60 AD59 17 18 AD58 AD57 19 20 GND V I O 21 22 AD56 AD55 23 24 AD54 AD53 25 26 GND GND 27 28 AD52 AD51 29 30 AD50 AD49 31 32 GND GND 33 34 AD48 AD47 35 36 AD46 AD45 37 38 GND V I O 39 40 AD44 AD43 41 42 AD42 AD41 43 44 GND GND 45 46 AD40 AD39 47 48 AD38 AD37 49 50 GND GND 51 52 AD36 AD35 53 54 AD34 AD33 55 56 GND V...

Page 47: ...ssignments J14 Signal Pin Pin Signal XMC1_PMC1_01 1 2 PMC1IO_02 PMC1IO_03 3 4 PMC1IO_04 PMC1IO_05 5 6 PMC1IO_06 PMC1IO_07 7 8 PMC1IO_08 PMC1IO_09 9 10 PMC1IO_10 PMC1IO_11 11 12 PMC1IO_12 PMC1IO_13 13 14 PMC1IO_14 PMC1IO_15 15 16 PMC1IO_16 PMC1IO_17 17 18 PMC1IO_18 PMC1IO_19 19 20 PMC1IO_20 PMC1IO_21 21 22 PMC1IO_22 PMC1IO_23 23 24 PMC1IO_24 PMC1IO_25 25 26 PMC1IO_26 PMC1IO_27 27 28 PMC1IO_28 PMC1I...

Page 48: ... with a PCIe PCI bridge Pericom PI7C9X130 The PCI bridge and PMC2 bus is disabled when the PMC card is not installed or an XMC card is installed at this slot The PMC disabling can be overruled by UEFI Firmware Setup adjustments LINK See the User Manual for AMI UEFI Firmware Setup www ami com The PMC is electrically and mechanically compliant to the specification IEEE 1386 and 1386 1 with enhanceme...

Page 49: ...NTD 09 10 PCI Reserved GND 11 12 PCI Reserved 3V3 PCICLK 13 14 GND GND 15 16 GNT0 REQ0 17 18 5 V V I O 19 20 AD31 AD28 21 22 AD27 AD25 23 24 GND GND 25 26 CBE3 AD22 27 28 AD21 AD19 29 30 5 V V I O 31 32 AD17 FRAME 33 34 GND GND 35 36 IRDY DEVSEL 37 38 5 V PCIXCAP 39 40 LOCK SDONE 41 42 SBO PAR 43 44 GND V I O 45 46 AD15 AD12 47 48 AD11 AD9 49 50 5 V GND 51 52 CBE0 AD6 53 54 AD5 AD4 55 56 GND V I O...

Page 50: ...d PUP a 11 12 3 3 V PCIRST 13 14 PDN1a 3 3 V 15 16 PDN2a PME 17 18 GND AD30 19 20 AD29 GND 21 22 AD26 AD24 23 24 3 3 V IDSEL 25 26 AD23 3 3 V 27 28 A20 AD18 29 30 GND AD16 31 32 CBE2 GND 33 34 IDSELB TRDY 35 36 3 3 V GND 37 38 STOP PERR 39 40 GND 3 3 V 41 42 SERR CBE1 43 44 GND AD14 45 46 AD13 M66EN 47 48 AD10 AD8 49 50 3 3 V AD7 51 52 REQB 3 3 V 53 54 GNTB Reserved 55 56 GND Reserved 57 58 Reserv...

Page 51: ... 10 PAR64 AD63 11 12 AD62 AD61 13 14 GND GND 15 16 AD60 AD59 17 18 AD58 AD57 19 20 GND V I O 21 22 AD56 AD55 23 24 AD54 AD53 25 26 GND GND 27 28 AD52 AD51 29 30 AD50 AD49 31 32 GND GND 33 34 AD48 AD47 35 36 AD46 AD45 37 38 GND V I O 39 40 AD44 AD43 41 42 AD42 AD41 43 44 GND GND 45 46 AD40 AD39 47 48 AD38 AD37 49 50 GND GND 51 52 AD36 AD35 53 54 AD34 AD33 55 56 GND V I O 57 58 AD32 Reserved 59 60 R...

Page 52: ...XMC2_PMC2_03 3 4 XMC2_PMC2_04 XMC2_PMC2_05 5 6 XMC2_PMC2_06 XMC2_PMC2_07 7 8 XMC2_PMC2_08 XMC2_PMC2_09 9 10 XMC2_PMC2_10 XMC2_PMC2_11 11 12 XMC2_PMC2_12 XMC2_PMC2_13 13 14 XMC2_PMC2_14 XMC2_PMC2_15 15 16 XMC2_PMC2_16 XMC2_PMC2_17 17 18 XMC2_PMC2_18 XMC2_PMC2_19 19 20 XMC2_PMC2_20 XMC2_PMC2_21 21 22 XMC2_PMC2_22 XMC2_PMC2_23 23 24 XMC2_PMC2_24 XMC2_PMC2_25 25 26 XMC2_PMC2_26 XMC2_PMC2_27 27 28 XMC2...

Page 53: ...tors 53 XMC2_PMC2_55 55 56 XMC2_PMC2_56 XMC2_PMC2_57 57 58 XMC2_PMC2_58 XMC2_PMC2_59 59 60 XMC2_PMC2_60 XMC2_PMC2_61 61 62 XMC2_PMC2_62 XMC2_PMC2_63 63 64 XMC2_PMC2_64 Table 5 15 PMC2 I O Connector Pin Assignments J24 Continued Signal Pin Pin Signal ...

Page 54: ... 1 Figure 5 18 XMC Connector J15 and J16 A1 A19 F19 F1 Table 5 16 XMC1 Connector Pin Assignments J15 Pin Row A Row B Row C Row D Row E Row F 1 TX0 TX0 3 3 V TX1 TX1 5 V 2 GND GND TRST GND GND XMCRSTINa 3 TX2 TX2 3 3 V TX3 TX3 5 V 4 GND GND TCK GND GND XMC1_RSTOUTb 5 TX4 TX4 3 3 V TX5 TX5 5 V 6 GND GND TMS GND GND 12 V 7 TX6 TX6 3 3 V TX7 TX7 5 V 8 GND GND TDI GND GND 12 V 9 NC NC RPS NC NC 5 V 10 ...

Page 55: ...XMC1_PMC1_30 NC XMC1_PMC1_27 XMC1_PMC1_28 NC 6 GND GND NC GND GND NC 7 XMC1_PMC1_33 XMC1_PMC1_34 NC XMC1_PMC1_31 XMC1_PMC1_32 NC 8 GND GND XMC1_PMC1_01 GND GND XMC1_PMC1_02 9 XMC1_PMC1_39 XMC1_PMC1_40 XMC1_PMC1_03 XMC1_PMC1_37 XMC1_PMC1_38 XMC1_PMC1_04 10 GND GND XMC1_PMC1_05 GND GND XMC1_PMC1_06 11 XMC1_PMC1_43 XMC1_PMC1_44 XMC1_PMC1_07 XMC1_PMC1_41 XMC1_PMC1_42 XMC1_PMC1_08 12 GND GND XMC1_PMC1_...

Page 56: ...trically and mechanically compliant to the specification VITA 61 0 and IEEE 1386 1 Figure 5 19 XMC Connector J25 A1 A19 F19 F1 Table 5 18 XMC2 Connector Pin Assignments J25 Pin A B C D E F 1 TX0 TX0 3 3 V TX1 TX1 5 V 2 GND GND TRST GND GND XMCRSTINa 3 TX2 TX2 3 3 V TX3 TX3 5 V 4 GND GND TCK GND GND XMC2_RSTOUTb 5 NC NC 3 3 V NC NC 5 V 6 GND GND TMS GND GND 12 V 7 NC NC 3 3 V NC NC 5 V 8 GND GND TD...

Page 57: ...MC2_PMC2_31 XMC2_PMC2_32 NC 8 GND GND XMC2_PMC2_01 GND GND XMC2_PMC2_02 9 XMC2_PMC2_39 XMC2_PMC2_40 XMC2_PMC2_03 XMC2_PMC2_37 XMC2_PMC2_38 XMC2_PMC2_04 10 GND GND XMC2_PMC2_05 GND GND XMC2_PMC2_06 11 XMC2_PMC2_43 XMC2_PMC2_44 XMC2_PMC2_07 XMC2_PMC2_41 XMC2_PMC2_42 XMC2_PMC2_08 12 GND GND XMC2_PMC2_09 GND GND XMC2_PMC2_10 13 XMC2_PMC2_49 XMC2_PMC2_50 XMC2_PMC2_11 XMC2_PMC2_47 XMC2_PMC2_48 XMC2_PMC2...

Page 58: ...IO_13 PMC1IO_12 PMC1IO_11 GND 10 PMC1IO_20 PMC1IO_19 PMC1IO_18 PMC1IO_17 PMC1IO_16 GND 11 PMC1IO_25 PMC1IO_24 PMC1IO_23 PMC1IO_22 PMC1IO_21 GND 12 PMC1IO_30 PMC1IO_29 PMC1IO_28 PMC1IO_27 PMC1IO_26 GND 13 PMC1IO_35 PMC1IO_34 PMC1IO_33 PMC1IO_32 PMC1IO_31 GND 14 PMC1IO_40 PMC1IO_39 PMC1IO_38 PMC1IO_37 PMC1IO_36 GND 15 PMC1IO_45 PMC1IO_44 PMC1IO_43 PMC1IO_42 PMC1IO_41 GND 16 PMC1IO_50 PMC1IO_49 PMC1I...

Page 59: ...C1IO_19 PMC1IO_18 PMC1IO_17 PMC1IO_16 GND 11 CD_L CD_R PMC1IO_23 PMC1IO_22 LINE_OUT_L GND 12 CD_COM PMC1IO_29 PMC1IO_28 PMC1IO_27 LINE_OUT_R GND 13 PMC1IO_35 PMC1IO_34 PMC1IO_33 PMC1IO_32 PMC1IO_31 GND 14 VGA2_DDCD PMC1IO_39 PMC1IO_38 PMC1IO_37 PMC1IO_36 GND 15 VGA2_RED VGA2_GREEN VGA2_BLUE VGA2_HSYNC VGA2_DDCC GND 16 DVI2_TXC DVI2_TXC SATA3_RX SATA3_RX VGA2_VSYNC GND 17 DVI2_TX0 DVI2_TX0 DVI2_HPD...

Page 60: ...C1IO_11 GND 10 PMC1IO_20 PMC1IO_19 PMC1IO_18 PMC1IO_17 PMC1IO_16 GND 11 PMC1IO_25 PMC1IO_24 PMC1IO_23 PMC1IO_22 PMC1IO_21 GND 12 PMC1IO_30 PMC1IO_29 PMC1IO_28 PMC1IO_27 PMC1IO_26 GND 13 PMC1IO_35 PMC1IO_34 PMC1IO_33 PMC1IO_32 PMC1IO_31 GND 14 PMC1IO_40 PMC1IO_39 PMC1IO_38 PMC1IO_37 PMC1IO_36 GND 15 PMC1IO_45 PMC1IO_44 PMC1IO_43 PMC1IO_42 PMC1IO_41 GND 16 DVI2_TXC DVI2_TXC SATA3_RX SATA3_RX PMC1IO_...

Page 61: ...AP 10 GND VMESYSCLK VMEBG3IN VMESYSFAIL GA0 11 Reserved GND VMEBG3OUT VMEBERR GA1 12 GND VMEDS1 VMEBR0 VMESYSRES ET 3 3 V 13 Reserved VMEDS0 VMEBR1 VMELWORD GA2 14 GND VMEWRITE VMEBR2 VMEAM5 3 3 V 15 Reserved GND VMEBR3 VMEA23 GA3 16 GND VMEDTACK VMEAM0 VMEA22 3 3 V 17 Reserved GND VMEAM1 VMEA21 GA4 18 GND VMEAS VMEAM2 VMEA20 3 3 V 19 Reserved GND VMEAM3 VMEA19 SMB_SCL 20 GND VMEIACK GND VMEA18 3 ...

Page 62: ...C2_13 DVI1TX2 GPIO6 8 GND XMC2_PMC2_16 VMEA28 XMC2_PMC2_15 DVI1TX2 GPIO7 9 HW_WP_L XMC2_PMC2_18 VMEA29 XMC2_PMC2_17 DVI1HPD _IN_L 10 GND XMC2_PMC2_20 VMEA30 XMC2_PMC2_19 PWR_BUT 11 OC2_USB_L XMC2_PMC2_22 VMEA31 XMC2_PMC2_21 CODEC_PCBEEP 12 GND XMC2_PMC2_24 GND XMC2_PMC2_23 DDCC_DVI1 GPIO8 13 RESET_LED_L XMC2_PMC2_26 5 V XMC2_PMC2_25 DDCD_DVI1 GPIO9 14 GND XMC2_PMC2_28 VMED16 XMC2_PMC2_27 GPIO10 15...

Page 63: ...voltage Recovery from this catastrophic event can be accomplished with a power off on cycle or Power Button Figure 6 1 Block Diagram 4 8 GByte DDR3L HARD DRIVE option IPMI w power monitoring BIOS BIT Backup BIOS P0 P2 P1 GbE Gb E PMC XMC2 IO P2 SATA2 SATA3 not available if rear USB 3 0 selected DVI D 2 USB 2 0 USB 2 0 DVI D 1 COM 1 COM 2 GPIO VGA 1 P0 P0 GPIO P2 COM2 P2 COM1 P2 SPI DMI LPC COM3 Gb...

Page 64: ...ory controllers with ECC and SPD DDR3L 1600 MHz See Section 6 3 CPU Memory Controller Internal 3D Graphics processor 6 1 2 Processor Supported Technologies Graphics support for DX11 1 OpenCL1 2 Open GL3 2 Intel Hyper Threading Technology Intel HT Technology two threads per core Intel 64 architecture Intel Turbo Boost Technology Intel Advanced Vector Extensions Default disabled AVX 2 0 extensions A...

Page 65: ...pports Intel Virtualization Technology for Directed I O Four digital ports are supported in the CPU DisplayPort Embedded DisplayPort Drives EDP to VGA Two DVI ports Serial Peripheral Interface SPI support Support for TXT Trusted Execution Technology 6 3 CPU Memory Controller The CPU integrated dual channel memory controller in the XVR16 supports dual data rate synchronous DRAM DDR3 with a data bus...

Page 66: ... is connected to the rear P2 VGA2 Analog VGA port from the integrated RAMDAC supports up to 180 MHz with a resolution of 1920x2000 at 60 Hz This port is connected to the rear P0 NOTE The termination 75 Ohm to ground resistors must be located at a possible interface board i e Transition Module VTM26 DVI 1 when chosen as an option is connected to DisplayPort C of the PCH The maximum pixel rate is 16...

Page 67: ...ress Channels 4th Generation Core i7 CPU Root Complex x8 PCIe port connects to XMC site 1 via mux Lower x4 muxed to PCIe to PCI X bridge to PMC site 1 One x4 PCIe port muxed between XMC site 2 and PCIe to PCI X bridge to PMC site 2 One x4 PCIe port to PCIe to PCI X bridge to TSI148 VME bridge 3 0 7 4 11 8 15 12 CPU PCIe x4 MUX Bridge PMC x8 x4 x4 x4 XMC PMC VME PMC XMC Site1 PMC XMC Site2 x4 x4 x4...

Page 68: ...sity of an extra system controller The VME controller is connected via a 64 bit PCI X 133 MHz PCIe to PCI bridge Pericom PI7c9x130 6 7 1 VMEbus Features 64 bit 133 MHz PCI X local bus interface Integral FIFOs for write posting and read pre fetching to maximize bandwidth utilization Programmable DMA controller with linked list support Complete suite of VMEbus address and transfer modes Master inclu...

Page 69: ... semaphores But regardless of the method used when using shared memory the user must gain exclusive VME ownership prior to generating asynchronous VME writes Extremely Long VME Slave Response Time VME slave devices or VME BERR conditions that have a DTACK or BERR response time of greater than 16 can cause Bridge Ordering rule issues with intermixed reads and writes through the Tsi148 If the SBC us...

Page 70: ...o decide whether the VME SYSRESET should be used as an input 6 8 Interrupt Controller The Mobile Intel QM87 Express Chipset provides an ISA compatible Programmable Interrupt Controller PIC that consists of two 82C59A devices with eight interrupt request lines each The two controllers are cascaded so that fourteen external and two internal interrupt sources are available The master interrupt contro...

Page 71: ...th 1 second resolution and 242 bytes of general purpose CMOS RAM used by system UEFI Firmware The three maskable interrupts features are Time of day alarm with once a second to once a month range Periodic rates of 122 s to 500 ms End of update cycle notification The lower 14 bytes on the lower RAM block has very specific functions The first ten are for time and date information The next four 0Ah t...

Page 72: ...I Firmware with automatic swap Integrated VGA and Ethernet PXE ROM BIOS USB mass storage support password protection headless support Remote console via serial port 6 12 BMC A Baseboard Management Controller BMC is implemented on the XVR16 interfacing between the host processor and the system management network This controller can also function as a Peripheral Management PM Controller The BMC is m...

Page 73: ...re manual for details LINK For more details on the ETI device see www maxim ic com 6 14 Keyboard and Mouse The communication between the PC and the keyboard and mouse is managed by a USB connection A legacy 8042 interface is available via emulation for USB unaware OS 6 15 SATA Interface The XVR16 offers up to six SATA Gen1 and Gen2 channels that can transfer up to 300 MByte s SATA Ports SATA0 to o...

Page 74: ... capability Each network interface is assigned a unique MAC address which resides in an Ethernet address ROM on the XVR16 All GbE interfaces are equipped with LEDs indicating Link and Activity Two GbE interfaces available at the front panel ETH1 Intel Springville standard port ETH2 Intel Springville optionally provided when the PMC XMC option is not chosen H 1 2 or 3 Two GbEs at the rear are route...

Page 75: ...Memory page selection is controlled by the MRAM register located at IO Space 0x68A See Table 8 15 for additional details on MRAM Page Registers Timers The XVR16 FPGA provides two 32 bit timers with load continuous and one shot modes and interrupt capability See Table 8 16 Table 8 17 Table 8 23 and Table 8 24 GPIO 0 11 The GPIO is sourced from the FPGA Twelve GPIO pins are available on the VME conn...

Page 76: ...es Representative for BIT availability Five LEDs plus two user programmable LEDS are available at the front panel Two status lines for LEDs are connected to the rear See Section 5 1 Front Panel Interface on page 36 Front I O LEDs 1x Front Power Good Green LED 1x Front Aux_Power_Good Red LED 1x Front Reset Status Red LED 1x Front BITFail Red LED 2x Front Yellow user programmable LEDs 1x Front BITPa...

Page 77: ... without operating system support State S5 switches off the CPU core power and holds the XVR16 in reset The state S5 is indicated at the S State LED At this state it is possible to reactivate the XVR16 with a short press at the PWR Button The CPU core voltage is switched on and the board restarts This power off and power on cycle can be used to reset the XVR16 6 17 6 HD Audio High Definition HD Au...

Page 78: ...1 Memory Mapping The table below shows the memory address area used by the XVR16 Table 7 1 Memory Mapping Address Size Used by 0 9_FFFF 640 KByte System RAM A_0000 B_FFFF 128 KByte Video RAM if enabled C_0000 D_FFFF 128 KByte Used by PCI ROMs Add on cards E_0000 F_FFFF 128 KByte UEFI Firmware 10_0000 EFFF_FFFF Depends on available DRAM Extended RAM 4000_0000 FFBF_FFFF Depends on available DRAM Dyn...

Page 79: ...le below provides an overview of the address ranges occupied by these registers Table 7 2 Standard Register Settings I O Address Range Hex Function 00H 0FH DMA Controller 20H 21H Interrupt Controller 40H 43H Counter Timer 60H Keyboard Controller 61H NMI Status and Control 64H Keyboard Controller 70H 71H RTC NMI Mask 80H 8FH DMA Page Register A0H A1H Interrupt Controller B2H B3H Power Management C0...

Page 80: ...2 Cascade from INTC2 IRQ03 COM2b IRQ04 COM1b IRQ05 GPIO0 11 IRQ06 Timers 1 and 2 IRQ07 COM3b IRQ08 Real Time Clock IRQ09 Power Management Control IRQ10 COM4b IRQ11 PnP PCIb IRQ12 PS 2 Mouse a IRQ13 Numeric Coprocessor IRQ14 External IDE c IRQ15 Onboard IDE d NMI Parity Error ECC Error System Error a Emulated interrupt from USB keyboard mouse b Interrupts are available for Plug and Play PCI devices...

Page 81: ...IC transmits interrupts through processor FSB and interrupts are handled without the need for the processor to run an interrupt acknowledge cycle Interrupt Priority The priority of interrupts in the I O APIC is independent of the interrupt number For example interrupt 10 may be given a higher priority than interrupt 3 More Interrupts The three I O APICs in the XVR16 support a total of twenty four ...

Page 82: ...ntrolling multiple events Software controlled general purpose timers GPIO signals sourcing Write protection control The XVR16 provides bootable NAND Flash and 512 KByte of nonvolatile random access memory NVRAM The block diagram for the FPGA is shown in the figure below Figure 8 1 Block Diagram for FPGA RT LPC Interface LFRAME LAD 3 0 PCI CL K RESET IO addr 0x600 32 bit Timer 32 bit Timer WDT Boar...

Page 83: ...evision Read 60C Reserved NA 60D Watchdog Timers WDT Refresh Read Write 60E Watchdog Timer CSR LSB Read Write 60F Watchdog Timer CSR MSB Read Write 610 to 61A Board ID String Read 61B Reset Cause Register 1 Read 61C Reset Cause Register 2 Read 61D 61F Reserved NA 620 BMM BMC Control Read Write 621 Reserved NA 622 LED Control Read Write 623 Reserved NA 624 Reserved NA 625 BIOS SPI Control Read Writ...

Page 84: ... 0 Available Read 679 67B Reserved NA 67C GPIO 15 8 Out Read Write 67D GPIO 15 8 In Read 67E GPIO 15 8 Direction Read Write 67F GPIO 15 8 Interrupt Enable Read Write 680 GPIO 15 8 Level Edge Read Write 681 GPIO 15 8 Active Low High Read Write 682 GPIO 15 8 Both Edges Read Write 683 GPIO 15 8 Interrupt Status Read Write to Clear 684 GPIO 15 8 Available Read 685 687 Reserved NA 688 696 Reserved NA 6...

Page 85: ...Enables Read Write 6BF SSD Erase Control Register Read Write 6C0 SSD Cache Flush Control Register Read Write 6C1 Reserved NA 6C2 VME Backplane Control Read Write 6C3 Reserved NA 6C4 6C5 Reserved NA 6C6 Scratch Pad Register 6C7 Test Register Reserved for Factory Test Only Read Write 6C8 PMC XMC1 Status NA 6C9 PMC XMC2 Status Read 6CA VME Backplane Status Read 6CB SSD Status Read 6CC Write Protectio...

Page 86: ...fter the WDT is enabled to keep the WDT from causing a Board Reset 0x00 Table 8 6 Watchdog Timer Control Status Register CSR LSB 0x60E Bit R W Description Default 7 1 R Reserved 0 0 R W Watchdog Timer Count Enable 1 WDT enabled 0 WDT disabled 0 Table 8 7 Watchdog Timer Control Status Register CSR MSB 0x60F Bit R W Description Default 7 3 R Reserved 0 2 0 R W Watchdog Timer Timeout Selection 111 WD...

Page 87: ...eserved 0 0 R VME Reset 0 Table 8 10 Reset Cause Register 2 0x617 Bit R W Description Default 7 4 R Reserved 0 3 R Reserved for BMC reset 0 2 1 R Reserved 0 0 R Watchdog Reset 0 Table 8 11 BMM BMC Control Register 0x620 Bit R W Description Default 7 6 R Reserved for BMM Not Required for BMC 0 5 R W BMC Interrupt Enable 1 Enable 0 Disable 0 4 0 R Reserved for BMM Not Required for BMC 0 ...

Page 88: ...n on the backplane 0 5 R W BIT Status 1 LED 1 LED ON 0 LED OFF 0 4 R W BIT Status 0 LED 1 LED lit 0 LED not lit 0 3 R Reserved for Standby Power LED 0 2 R W Board Power Status LED 1 LED ON 0 LED OFF 0 1 R W Reset Status LED 1 LED ON 0 LED OFF 0 0 R W SATA Status LED 1 LED ON 0 LED OFF 0 Table 8 13 BIOS SPI Control Register 0x625 Bit R W Description Default 7 R W Select Other boot device 1 Opposite...

Page 89: ...ET req 3 R W FAST BIT enable 1 Fast BIT enabled via BIOS setting 0 Fast BIT disabled 0 2 R W FAST Start enable 1 Fast Start enabled Via BIOS setting 0 Fast Start Disabled 0 1 R FAST Start Input GPIO0 1 0 R W BIT Run 1 BIT has been run 0 BIT not been run 0 sticky when reset using HRESET req Table 8 15 NVRAM Memory Space Page Register 0x635 Bit R W Description Reserved 7 3 R Reserved 0 2 0 R W 64K B...

Page 90: ... 2 CSR2 0x651 Bit R W Description Default 7 5 R Reserved NA 4 R W Timer Read Latch Select 1 Latch All Timers on read of Timer 0 LSB 0 Latch Individual Timers on the read of individual Timer LSB Note Setting this bit in any timer CSR2 register will have the same effect of latching ALL timers on read of timer 0 LSB 0 3 2 R Reserved NA 1 R W Timer One Shot Enable 1 Timer will count down once and stop...

Page 91: ... Reading this register latches the upper bits of the count value to prevent rollover Write always updates Timer load value 0x00 Table 8 21 Timer 0 Data Byte 2 0x656 Bit R W Description Default 7 0 R W Read value depends on value of CSR1 3 If 0 Contains Bits 23 16 of the Timer current counter value If 1 Contains Bits 23 16 of the Timer load value Reading this register latches the upper bits of the ...

Page 92: ...n 2 MHz Clock Used 00 1 1 2 MHz 01 1 2 1 MHz 10 1 4 500 KHz 11 1 8 250 KHz 0 0 R W Enable Timer IRQ 1 IRQ Enabled 0 IRQ Masked 0 Table 8 24 Timer 1 Control and Status Register 2 CSR2 0x659 Bit R W Description Default 7 5 R Reserved 0 4 R W Timer Read Latch Select 1 Latch All Timers on read of Timer 0 LSB 0 Latch Individual Timers on the read of individual Timer LSB Note Setting this bit in any tim...

Page 93: ... updates Timer load value 0x00 Table 8 27 Timer 1 Data Byte 1 0x65D Bit R W Description Default 7 0 R W Read value depends on CSR1 3 If 0 Contains Bits 15 8 of the Timer current counter value If 1 Contains Bits 15 8 of the Timer load value Reading this register latches the upper bits of the count value to prevent rollover Write always updates Timer load value 0x00 Table 8 28 Timer 1 Data Byte 2 0x...

Page 94: ...er current counter value If 1 Contains Bits 31 24 of the Timer load value Reading this register latches the upper bits of the count value to prevent rollover Write always updates Timer load value 0x00 Table 8 30 GPIO 7 0 OUT Register 0x670 Bit R W Description Default 7 0 R W GPIO7 GPIO0 0x00 Table 8 31 GPIO 7 0 IN Register 0x671 Bit R W Description Default 7 0 R W GPIO7 GPIO0 0x00 Table 8 32 GPIO ...

Page 95: ...Description Default 7 0 R W GPIO7 GPIO0 1 Edge 0 Level 0x00 Table 8 35 GPIO 7 0 Interrupt Active High Low Register 0x675 Bit R W Description Default 7 0 R W GPIO7 GPIO0 1 Active high rising edge 0 Active low falling edge Note Function depends on whether the bit is in level or edge mode 0x00 Table 8 36 GPIO 7 0 Both Edge Register 0x676 Bit R W Description Default 7 0 R W GPIO7 GPIO0 1 Both edge mod...

Page 96: ...ity Register 0x678 Bit R W Description Default 7 R GPIO7 Availability 1 GPIO7 Available 0 GPIO7 Not Available NA 6 R GPIO6 Availability 1 GPIO6 Available 0 GPIO6 Not Available NA 5 R GPIO5 Availability 1 GPIO5 Available 0 GPIO5 Not Available NA 4 R GPIO4 Availability 1 GPIO4 Available 0 GPIO4 Not Available NA 3 R GPIO3 Availability 1 GPIO3 Available 0 GPIO3 Not Available NA 2 R GPIO2 Availability ...

Page 97: ... Table 8 42 GPIO 15 8 Interrupt Enable Register 0x67F Bit R W Description Default 7 0 R W GPIO15 GPIO8 1 Interrupt enabled 0 Interrupt masked 0x00 Table 8 43 GPIO 15 8 Interrupt Level Edge Register 0x680 Bit R W Description Default 7 0 R W GPIO15 GPIO8 1 Edge 0 Level 0x00 Table 8 44 GPIO 15 8 Interrupt High Low Register 0x681 Bit R W Description Default 7 0 R W GPIO15 GPIO8 1 Active high rising ed...

Page 98: ...t pending 0 No interrupt 0x00 Table 8 47 GPIO 15 8 Availability Register 0x684 Bit R W Description Default 7 R GPIO15 Availability 1 GPIO15 Available 0 GPIO15 Not Available NA 6 R GPIO14 Availability 1 GPIO14 Available 0 GPIO14 Not Available NA 5 R GPIO13 Availability 1 GPIO13 Available 0 GPIO13 Not Available NA 4 R GPIO12 Availability 1 GPIO12 Available 0 GPIO12 Not Available NA 3 R GPIO11 Availa...

Page 99: ...ster 0x6A3 Bit R W Description Default 7 0 R COM Port 8 1 Modem Configuration 1 Full modem line support is available 0 Full modem line support is not available NA Table 8 52 SATA Port Availability Register 0x6A4 Bit R W Description Default 7 0 R SATA Ports 7 0 availability 1 SATA ports are available 0 SATA ports are not available NA Table 8 53 USB 2 0 Port 7 0 Availability Register 0x6A5 Bit R W D...

Page 100: ... 0 ports 15 8 availability 1 USB3 0 ports are available 0 USB3 0 ports are not available NA Table 8 57 Display Availability Register 0x6A9 Bit R W Description Default 7 0 R Display 7 0 availability 1 Display is available 0 Display is not available NA Table 8 58 VGA Display Availability Register 0x6AA Bit R W Description Default 7 0 R Display 7 0 VGA availability 1 Display is VGA type 0 Display is ...

Page 101: ...available NA Table 8 61 Front Panel Configuration Register 0x6AE Bit R W Description Default 7 R Ethernet port 1 present on front panel 1 Ethernet Port1 present 0 Ethernet Port1 not present NA 6 R SATA port 1 present on front panel 1 SATA Port1 present 0 SATA Port1 not present NA 5 R USB 2 0 port 1 present on front panel 1 USB2 0 Port1 present 0 USB2 0 Port1 not present NA 4 R Video port 1 present...

Page 102: ... XMC X24s configuration 1 I O is X24s compliant 0 I O is not X24s compliant NA 0 R XMC X38s configuration 1 I O is X38s compliant 0 I O is not X38s compliant NA Table 8 63 XMC PMC2 I O Configuration Register 0x6B0 Bit R W Description Default 7 R P64s compliant configuration 1 I O is P64 compliant 0 I O is not P64 compliant NA 6 R Reduced P64s configuration 1 I O is a subset of P64 0 I O is not a s...

Page 103: ...ithm being executed Hardware Secure Erase not currently available but maybe in the future 0x00 Table 8 66 UART Enable Register 0x6B8 Bit R W Description Default 7 0 R W COM8 1 UART Enable 1 UART is enabled 0 UART is disabled and will not respond to reads or writes NA Table 8 67 COM Port Transceiver Enable Register 0x6BB Bit R W Description Default 7 0 R W COM8 1 Enable 1 COM Port transceivers enab...

Page 104: ...e port Otherwise the transceiver is tri stated 0 COM Port RS485 Auto Direction Control disabled Note This bit can only be set to a 1 when the corresponding bit in the COM port Mode register 0x6BC is set to RS422 mode 0x00 Table 8 70 COM Port Loopback Enable Register 0x6BE Bit R W Description Default 7 0 R W COM8 1 Loopback Enable 1 COM Port transceiver loopback mode enabled 0 COM Port transceiver ...

Page 105: ...sence 1 XMC1 is fitted 0 XMC1 is not fitted NA 6 R XMC1 VPWR voltage 0 XMC1 VPWR rail is 5 V 1 XMC1 VPWR rail is 12 V NA 5 R XMC1 BIST status 1 XMC1 BIST is active 0 XMC1 BIST is not active NA 4 3 R Reserved NA 2 R PMC1 enumeration ready status 1 PMC1 ERDY pin is active OK to enumerate 0 PMC1 ERDY pin is not active NA 1 R PMC1 VIO voltage 1 PMC1 VIO voltage 5 V 0 PMC1 VIO voltage 3 3 V NA 0 R PMC1...

Page 106: ...PWR rail is 12 V NA 5 R XMC2 BIST status 1 XMC2 BIST is active 0 XMC2 BIST is not active NA 4 3 R Reserved NA 2 R PMC2 enumeration ready status 1 PMC2 ERDY pin is active OK to enumerate 0 PMC2 ERDY pin is not active NA 1 R PMC2 VIO Voltage 1 PMC2 VIO voltage 5 V 0 PMC2 VIO voltage 3 3 V NA 0 R PMC2 Presence 1 PMC2 is fitted 0 PMC2 is not fitted NA Table 8 76 SSD Status Register 0x6CB Bit R W Descr...

Page 107: ...ected 0 4 R Reserved 0 3 R Boot SPI status 1 Write protected 0 Not Write protected 0 2 R Recover Boot SPI status 1 Write protected 0 Not Write protected 0 1 R NVRAM status 1 Write protected 0 Not Write protected 0 0 R Reserved 0 Table 8 78 Board Jumper Link Status Register 0x6CD Bit R W Description Default 7 R NVRAM Link status 1 Link is installed 0 Link is not installed 0 6 R Recovery boot link s...

Page 108: ...ted onboard Determined by the state of the TAC SPD jumper link on the test card 0 3 R Ethernet configuration ROM location 1 Board booted using ethernet configuration ROM on test card 0 Board booted using ethernet configuration ROM onboard 0 2 0 R Reserved 0 Table 8 80 Thermal Status Register 0x6D0 Bit R W Description Default 7 R Reserved 0 6 R Ambient board temperature thermal alarm 1 Thermal alar...

Page 109: ... available in accordance with MIL HDBK 217 Levels TIP Refer to Appendix D Processor Speed and Temperature for more information on High Temperature WARNING The ambient high temperature is dependent on the CPU that is used the air flow and other conditions See Section 9 4 Environmental Conditions on page 113 for more details Table 9 1 Levels Available XVR16 Level 1 Level 2 Level 3 Level 4 Level 5 Lo...

Page 110: ...onboard hard disk drive add the following values to the 5 V current During power up 0 9 A max In an idle condition 0 13 A typical During read write access 0 42 A typical NOTE Values derived from the Fujitsu MHT 2060 AT data sheet For keyboard mouse etc add 0 1 A typical to the 5 V current USB connector P1680 provides fused VCC voltage 5 V The total current drawn from this source may not exceed 1 0...

Page 111: ...ry and operating mode XVR16 power on RTC supplied by power rail The XVR16 RTC has a current consumption of 6 A board non operating NOTE Batteries are installed in convection cooled version boards Levels 1 and 2 Levels 3 4 and 5 do not have batteries installed 9 2 1 Battery Lifetime The battery lifetime varies with the temperature range Table 9 3 Battery Lifetime Mode Temperature Range Lifetime in ...

Page 112: ...bottom of the battery on the solder side of the board This pushes the battery up allowing more of it to be exposed on the component side of the board 2 The battery can then be grasped at the top and removed from the socket Replacement A new battery can be installed by sliding it into the holder Make sure to observe correct polarity 1 Observe the proper polarity 2 Push the new battery down into the...

Page 113: ...nt consumption 9 4 Environmental Conditions Ambient temperatures and humidity values for the XVR16 NOTE Refer to Appendix D Processor Speed and Temperature for more information on Maximum Operating Temperature 3 dB octave roll off from 5 to 20 Hz and 6 dB octave roll off from 1000 to 2000 Hz No roll off Table 9 4 5VSTDBY Current Consumption 5VSTDBY RTC IPMI XVR16 operating mode 0 mA 0 mA XVR16 non...

Page 114: ...istics The XVR16 requires supply voltages of 5 V and 3 3 V 12 and 12 V are only required if needed on the PMC slot The table below shows voltages with maximum current restrictions due to layout restrictions or fusing 9 5 1 Supply Voltage Range The following ranges are defined by the VME64 specification ANSI VITA 1 1994 for VME64 and ANSI VITA 1 1 1997 for VME64 Extensions The voltages must be meas...

Page 115: ...ge By itself the onboard digital ground GND and the front panel chassis frame ground FGND are isolated on the XVR16 with a layout distance of more than 0 3 mm in all PCB layers However most standard devices keyboard mouse and monitor except Ethernet connects FGND and GND directly in the device Also standard racks connect both grounds at the power supply for safety reasons Table 9 9 GPIO IN Signal ...

Page 116: ...vailable in any XVR16 board version The VTM26 provides these signals at a 15 pin SUB D connector The connector is available only if a hard disk is not mounted The RGB signals are terminated with 75 Ohm resistors at the transition module P4100 VGA1 VGA2 COM2 COM1 DVI1 2 PWR P2 P0 USB USB0 USB1 eSATA1 SATA3 SATA4 ETH3 ETH4 1 1 1 1 1 1 1 1 1 1A 1B 1C 1D 1Z 1 7 7 C C A A SATA5 Onboard HD SPDIF Audio O...

Page 117: ...odule The signals are shared with PMC2 I O signals For availability the correct version of XVR16 and VTM26 must be selected Table A 1 VGA1 Interface P4100 P4100 Name 1 VGA1_RED 2 VGA1_GREEN 3 VGA1_BLUE 4 NC 9 5 V 11 NC 12 VGA1_DDCData 13 VGA1_HSYNC 14 VGA1_VSYNC 15 VGA1_DDCClock 5 6 7 8 10 GND VTM26 Table A 2 VTM26 VGA2 P4300 P4300 Name 2 VGA2_RED 4 VGA2_GREEN 6 VGA2_BLUE 8 VGA2_HSYNC 10 VGA2_VSYN...

Page 118: ...D for COM2 is available only if a hard disk is not mounted at the transition module The ports are software selectable for RS232 or RS422 485 operation The RS485 output drivers can be enabled or disabled with the DTR signal An active DTR means the drivers are always enabled When using the RS422 setting the output drivers are always enabled and the DTR signal is not used NOTE 2100 is har Link P2200 ...

Page 119: ...nterface 10 100 1000BASE T The Ethernet interfaces for rear I O requires usage of CAT 5 cable for proper operation with 100 1000BASE T Table A 4 VTM26 COM2 P2200 P2201 P2200 P2201 Name RS232 Name RS422 RS485 1 1 DCD TXD 6 2 DSR TXD 2 3 RXD RTS 7 4 RTS RTS 3 5 TXD CTS 8 6 CTS CTS 4 7 DTR RXD 9 8 RI RXD 5 9 GND 10 5 V Table A 5 VTM26 Ethernet Connectors P5300 P5400 Ethernet 3 4 10 100BASE 1000BASE 1...

Page 120: ...tors P1600 P1601 Two channels are available at the standard USB connectors FUSE_VCC is fused with 2 A however for normal operation do not exceed 1 A at this pin Figure A 5 USB Connectors P1600 P1601 Table A 6 VTM26 LEDs LED Function Right green LED On Link is active Off No link Left yellow LED On blink Tx Rx activity Off No activity Table A 7 VTM26 USB0 P1600 Name P1600 FUSE_VCC 1 USB0 2 USB0 3 GN...

Page 121: ...s only a cable connector P1740 SATA5 has either an eSATA connector P1751 or a connector for direct mounting P1750 a hard disk at the transition module In this case the front connector for COM2 and VGA1 are not available Figure A 6 eSATA5 Connector Table A 9 SATAxx eSATA Pin Name 2 SATATXx 3 SATATXx 5 SATARXx 6 SATARXx 1 4 7 GND Table A 10 SATA5 HD Direct Signal section Name 2 SATATX5 3 SATATX5 5 S...

Page 122: ...DVI connector with the number ʺ1ʺ Since DVI1 signals are shared with GPIO 0 9 and DVI2 signals are shared with PMC2 I O the correct XVR16 version must be selected for availability Figure A 8 DMS59 Connector Layout VTM26 DMS59 Connector Digital Pin Assignments Table A 11 VTM26 DMS59 Connector Digital Pin Assignments DVI1 and DVI2 Pin Signal name Pin Signal name 1 GND 31 DVI2_TXC 2 NC 32 DVI2_TXC 3 ...

Page 123: ... GND 17 DVI1_TX0 47 NC 18 DVI1_TX1 48 NC 19 DVI1_TX1 49 GND DVI1_Clock Shield 20 DVI1_TX2 50 NC 21 DVI1_TX2 51 NC 22 GND 52 GND 23 NC 53 NC 24 GND 54 GND 25 DVI2_TX2 55 NC 26 DVI2_TX2 56 NC 27 DVI2_TX1 57 GND DVI2_Clock Shield 28 DVI2_TX1 Key 29 DVI2_TX0 58 NC 30 DVI2_TX0 59 GND Table A 12 GPIO Connector P2002 P2002 Name 3 GPIO0 5 GPIO1 7 GPIO2 9 GPIO3 11 GPIO4 13 GPIO5 15 GPIO6 17 GPIO7 19 GPIO8 ...

Page 124: ...s pin A 1 9 Audio Pinouts The VTM26 provides audio connectors U1 for the audio signals and P2901 for SPDIFOUT Figure A 9 VTM26 Audio Pinouts Table A 13 VTM26 Miscellaneous Connector P2000 Name P2000 P2000 Name NC 1 2 NC HW_WP 3 4 STATLED BITFAILR 5 6 GND PWRBUT 7 8 GND SPEAKER 9 10 5 V Table A 14 U1 and P2901 Pinouts Pin Number Name U1 1 LINE_OUT_L 2 LINE_OUT_R 3 GND 4 LINE_IN_L 5 LINE_IN_R 6 GND ...

Page 125: ...7 8 PMCxIO_08 PMCxIO_09 9 10 PMCxIO_10 PMCxIO_11 11 12 PMCxIO_12 PMCxIO_13 13 14 PMCxIO_14 PMCxIO_15 15 16 PMCxIO_16 PMCxIO_17 17 18 PMCxIO_18 PMCxIO_19 19 20 PMCxIO_20 PMCxIO_21 21 22 PMCxIO_22 PMCxIO_23 23 24 PMCxIO_24 PMCxIO_25 25 26 PMCxIO_26 PMCxIO_27 27 28 PMCxIO_28 PMCxIO_29 29 30 PMCxIO_30 PMCxIO_31 31 32 PMCxIO_32 PMCxIO_33 33 34 PMCxIO_34 PMCxIO_35 35 36 PMCxIO_36 PMCxIO_37 37 38 PMCxIO_...

Page 126: ... XVR16 A 2 VTM28 Transition Module This section describes the VTM28 Transition Module This transition module would be used with the XVR16 in the special case that the XVR16 ordering configuration has H 0 and G 1 or 4 in order to provide support for PMC I O through two MEZZIO connectors for all of the XVR16 PMC I O sites If other signals are needed rather than PMC I O then it is recommended to purc...

Page 127: ...ication No 500 9300007876 000 Rev C 0 Transition Modules 127 Figure A 10 VTM28 Transition Module DVI J27 COM1 J100 USB0 USB1 LAN B LAN A J30 J29 J24 J23 COM2 P10 J31 VGA1 P2 P0 MEZZIO J21 WP J14 MEZZIO J22 ...

Page 128: ...ssible via the transition module COM1 is via a 10 pin har Link connector Use adapter cable YLB CR12 01 for the interface to the 9 pin SUB D connector COM2 is via a 9 pin SUB D connector The ports are software selectable for RS232 or RS422 RS485 operation The RS485 output drivers can be enabled or disabled with the DTR signal An active DTR means the drivers are always enabled When using the RS422 s...

Page 129: ...100 1000BASE T J29 J30 Figure A 13 Ethernet Interface 10 100 1000BASE T Table A 19 VTM28 COM1 J100 J100 har Link Name RS232 Name RS422 RS485 1 DCD TXD 2 DSR TXD 3 RXD RTS 4 RTS RTS 5 TXD CTS 6 CTS CTS 7 DTR RXD 8 RI RXD 9 GND 10 5 V Table A 20 VTM28 COM2 P10 P10 Name RS232 Name RS422 RS485 1 DCD TXD 6 DSR TXD 2 RXD RTS 7 RTS RTS 3 TXD CTS 8 CTS CTS 4 DTR RXD 9 RI RXD 5 GND ...

Page 130: ...4 Two channels are available at the standard USB connectors FUSE_VCC is fused with 2 A however for normal operation do not exceed 1 A at this pin Figure A 14 USB Connectors J23 J24 Table A 21 VTM28 Ethernet Connectors J29 J30 LAN A LAN B 10 100BASE 1000BASE 1 TxD DA 2 TxD DA 3 RxD DB 4 NC DC 5 NC DC 6 RxD DB 7 NC DD 8 NC DD Table A 22 VTM28 USB0 J23 Name J23 FUSE_VCC 1 USB0 2 USB0 3 GND 4 Table A ...

Page 131: ...nnector Due to layout reasons the VTM28 physical DVI1 port is connected with split cable DVI connector with number ʺ2ʺ DVI1 signals are shared with GPIO 0 9 Figure A 16 DMS59 Connector Layout VTM28 DMS59 Connector Digital Pin Assignments Table A 24 VTM28 DMS59 Connector Digital Pin Assignments for DVI Pin Signal name Pin Signal name 1 GND 31 NC 2 NC 32 NC 3 NC 33 GND 4 GND 34 GND 5 5 V 35 GND 6 NC...

Page 132: ...xceed 1 A at this pin 16 DVI1TX0 GPIO2 46 GND 17 DVI1TX0 GPIO3 47 NC 18 DVI1TX1 GPIO4 48 NC 19 DVI1TX1 GPIO5 49 GND 20 DVI1TX2 GPIO6 50 NC 21 DVI1TX2 GPIO7 51 NC 22 GND 52 GND 23 NC 53 NC 24 GND 54 GND 25 NC 55 NC 26 NC 56 NC 27 NC 57 GND 28 NC Key 29 NC 58 NC 30 NC 59 GND Table A 24 VTM28 DMS59 Connector Digital Pin Assignments for DVI Continued Pin Signal name Pin Signal name ...

Page 133: ...Cn_16 GND XMCn_PMCn_12 GND 8 GND XMCn_PMCn_13 GND XMCn_PMCn_09 GND XMCn_PMCn_14 GND XMCn_PMCn_10 GND 9 GND XMCn_PMCn_55 GND XMCn_PMCn_35 GND XMCn_PMCn_56 GND XMCn_PMCn_36 GND 10 GND XMCn_PMCn_45 GND XMCn_PMCn_25 GND XMCn_PMCn_46 GND XMCn_PMCn_26 GND 11 GND GND GND GND GND GND GND GND GND 12 GND XMCn_PMCn_24 GND XMCn_PMCn_20 GND XMCn_PMCn_22 GND XMCn_PMCn_18 GND 13 GND XMCn_PMCn_23 GND XMCn_PMCn_19...

Page 134: ...GND 10 GND GND GND GND GND GND GND GND GND 11 GND XMCn_PMCn_31 GND XMCn_PMCn_27 GND XMCn_PMCn_32 GND XMCn_PMCn_28 GND 12 GND XMCn_PMCn_29 GND XMCn_PMCn_25 GND XMCn_PMCn_30 GND XMCn_PMCn_26 GND 13 GND GND GND GND GND GND GND GND GND 14 GND XMCn_PMCn_39 GND XMCn_PMCn_35 GND XMCn_PMCn_40 GND XMCn_PMCn_36 GND 15 GND XMCn_PMCn_37 GND XMCn_PMCn_33 GND XMCn_PMCn_38 GND XMCn_PMCn_34 GND 16 GND GND GND GND...

Page 135: ...cted See the note at the end of section E 2 Non Volatile Memory on page 150 for additional information A 2 8 LED The rear status LED signals provide the board status at the VTM28 The signal already implemented the serial resistors on the XVR16 Table A 27 Rear BITFail Status LED BITFAIL_LED Status LED 1k Ohm serial resistor at XVR16 Built In Test Fail Red 1k Ohm serial resistor Table A 28 Rear Stat...

Page 136: ... to boot from This feature is useful when installing from a bootable disk For example when installing an operating system from a CD enter the First Boot menu and use the arrows keys to highlight ATAPI CD ROM Drive Press ENTER to continue with system boot This feature is accessed by pressing the F7 key at the very beginning of the boot cycle The selection made from this screen applies to the curren...

Page 137: ...a reserved for a text message When an option is selected in the left frame it is highlighted in white and a text message in the right frame gives a brief description of the option The Main menu reports the BIOS firmware revision and allows the user to set the system s clock and calendar Use the left and right arrow keys to select other screens NOTE Below is a sample of the Main screen The informat...

Page 138: ...ration to go to the sub menu for that item You can display an Advanced BIOS firmware Setup option by highlighting it using the Arrow keys A sample of the Advanced BIOS firmware Setup screen is shown below NOTE Changes in this screen can cause the system to malfunction If problems are noted after changes have been made reboot the system and access the BIOS firmware From the Exit menu select Load Fa...

Page 139: ...abling Disabling the GbE Boot from LAN BIOS Firmware The Gigabit Ethernet boot from LAN BIOS firmware provides support for booting over the network NOTE In order to boot from the network some operating systems require that the network driver be set to boot within the Control Panel The Gigabit Ethernet boot from LAN BIOS firmware defaults to Enabled in the BIOS firmware Setup Utility The Advanced M...

Page 140: ...n changing settings from the defaults set at the factory Below is a sample of the Chipset Setup screen the actual options on your system may vary NOTE Changes in this screen can cause the system to malfunction If problems are noted after changes have been made reboot the system and access the BIOS firmware From the Exit menu select Load Failsafe Defaults and reboot the system If the system failure...

Page 141: ...r Management Menu provides configuration options for watchdog timers and BIOS coordination and communication with the BMC The menu reports the status of communication with the BMC as may be used to display data collected from the BMC Self test information Event logs FRU data Table B 5 Server Mgmt Menu ...

Page 142: ...to set the priority of the boot devices including booting from a remote network The devices shown in this menu are the bootable devices detected during POST If a drive is installed that does not appear verify the hardware installation Also available in this screen are Boot Settings which allow the user to set how the basic system will act Table B 6 BIOS Boot Menu ...

Page 143: ...e set first The system can be configured so that all users must enter a password every time the system boots or when setup is executed using either the Supervisor password or User password Table B 7 BIOS Security Menu To reset the security in the case of a forgotten password you must clear the NVRAM and reconfigure Refer to Section 4 2 1 Clear CMOS RTC Password on page 33 for instructions on clear...

Page 144: ...he Save Exit BIOS firmware Setup screen You can display the Save Exit BIOS firmware Setup option by highlighting it using the Arrow keys The Save Exit BIOS firmware Setup screen is shown below Table B 8 BIOS Save Exit Menu If changes have previously been made in the BIOS firmware and the system malfunctions reboot the system and access this screen Select Restore Defaults and continue the reboot ...

Page 145: ...w these steps 1 Remove XVR16 from system housing 2 Remove the front panel cover of the PMC XMC slot 3 Take the PMC XMC from inside through the front panel and then press connectors together 4 Verify correct installation of the EMC gasket 5 Affix the PMC XMC onto the host boards with four screws Screws must be locked with Loctite 243 Table C 1 Electrical Characteristics Parameter Comment Value 5 V ...

Page 146: ...h optional Secondary Thermal Interfaces If the PMCs do not fit into their sockets on the XVR16 base board you can remove them Use a matching TORX screw driver to remove the Secondary Thermal Interfaces For mounting use a torque of 0 3 Nm to fix the screws or use minimum force to tighten the screws Add only a short turn 1 16th when the screw starts to tighten PMC EMC Gasket Front panel Connectors S...

Page 147: ...Publication No 500 9300007876 000 Rev C 0 Mezzanine Sites 147 Figure C 2 Mounting of Secondary Thermal Interface on PMC Module Screw M2 03 Nm Secondary Thermal Interface ...

Page 148: ... 4th Generation Intel Core i7 Based Rugged VME Single Board Computer Publication No 500 9300007876 000 Rev C 0 C 2 Installing HD ADAP8 SATA Module Figure C 3 Installing HD ADAP8 SATA Module HD ADAP8 SATA Module ...

Page 149: ...ata from the table above was taken while the units were running multi threaded test software used to stress the CPU memory and I O functions simultaneously This test load is generally heavier than a standard embedded application There may be some variance in the user s thermal results based on the end application Please contact Abaco Sales or Technical Support for any further thermal details or di...

Page 150: ...red upon power off Type of Memory Size User Modifiable User Data Access Function Process to Clear U192 NVRAM FRAM 55nS 3 3 V FRAM MRAM Ferroelectric Nonvolatile RAM 512 KByte Yes Yes Storage of user specific information This memory space can be cleared by any utility capable of writing IO Space U139 U140 U141 SPI Flash 3 3 V 16 MByte Yes Yes Contains BIOS code ME Firmware and BIOS settings This me...

Page 151: ...NTENTS ARE PROVIDED AS IS WITH NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO WARRANTIES OF DESIGN MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ALL OTHER LIABILITY ARISING FROM RELIANCE ON ANY INFORMATION CONTAINED HEREIN IS EXPRESSLY DISCLAIMED Abaco Systems Information Centers Americas 1 866 652 2226 866 OK ABACO or 1 256 880 0444 Inte...

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