abaco systems XVR16 Series, Hardware Reference Manual, Page: 104 / 151

104 XVR16*4th Generation Intel® Core™ i7 Based Rugged VME Single Board Computer Publication No. 500-9300007876-000 Rev. C.0
NOTE
To trigger a fast erase, enable bit must be written with a '1','0','1' pattern on consecutive write cycles to
this register. This is to protect against "accidental" erase functions. The value read from this register
represents the state of the output and not the last value written.
Table 8-69 COM Port RS485 Auto Direction Control Enable Register (0x6BD)
Bit R/W Description Default
7:0 R/W COM8:1 RS485 Auto Direction Control mode
1 = COM Port RS485 Auto Direction Control enabled.
When enabled, this mode causes the RTS signal to
assert and enable the transceiver whenever there is
data ready to be transmitted on the port. Otherwise, the
transceiver is tri-stated.
0 = COM Port RS485 Auto Direction Control disabled.
Note: This bit can only be set to a ‘1’ when the
corresponding bit in the COM port Mode register
(0x6BC) is set to “RS422 mode”.
0x00
Table 8-70 COM Port Loopback Enable Register (0x6BE)
Bit R/W Description Default
7:0 R/W COM8:1 Loopback Enable
1 = COM Port transceiver loopback mode enabled
0 = COM Port transceiver loopback mode disabled
(normal operation)
Loopback mode can be used by test software to test
the basic functionality of the transceiver.
0x00
Table 8-71 SSD Erase Control Register (0x6BF)
Bit R/W Description Default
7:0 R/W SSD7:0 Hardware erase
1 = Hardware Erase pin active
0 = Hardware Erase pin negated
0x00
Table 8-72 SSD Cache Flush Control Register (0x6C0)
Bit R/W Description Default
7:0 R/W SSD7:0 Cache Flush
1 = Cache Flush pin active
0 = Cache Flush pin negated
This bit directly controls the cache flush pin of the SSD
device.
0x00