26 CR12/CT12, VR12/VP12 UEFI Firmware User's Guide
Publication No. UGCR12V051E Rev. A.0
down at the rate of the PCI clock. When the counter reaches zero, the PCI device
releases the bus. If no other PCI device is waiting for bus ownership, it may take the
bus again and transfer more data.
For better PCI throughput, a longer latency should be used. In addition, time critical
applications may work better with shorter latencies. Customer should benchmark
his system performance to determine the optimal PCI Latency Timer.
4.4.4
VGA Palette Snoop
The optimal default is
Disabled
.
This setting is for old legacy reason. When enabled an appropriate device without its
own VGA palette (i.e. MPEG decoder) will snoop VGA palette data from the
graphics device to generate proper colors.
The user should not change setting unless your card manufacturer requires VGA
Palette Snooping to be enabled. A wrong setting may result in inaccurate colors on
the monitor.
4.4.5
PERR# Generation
The optimal default is
Disabled
.
Parity Error (PERR#) pin is asserted active by PCI (‐X,‐E) device
when a data parity
error is detected. When this option is enabled, PERR is logged and a NMI is
generated. Otherwise, when an error is detected, PERR is still logged but the PCI (‐
X,‐E) device will continue operation as normal and no NMI is
generated.
4.4.6
SERR# Generation
The optimal default is
Disabled
.
System Error (SERR#) pin is asserted active by PCI (‐X,‐E) device when a data error
or a system error is detected. When this option is enabled, SERR is logged and a NMI
is generated. Otherwise, when an error is detected, SERR is still
logged but the PCI (‐
X,‐E) device will continue operation as normal and no NMI is generated.
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