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PCM-6894 User Manual
Advanced Chipset Features
DRAM Timing By SPD
This item allows you to select the value in this field, depending
on whether the board has paged DRAMs or EDO (extended data
output) DRAMs.
The choices: Enabled, Disabled.
DRAM Clock
This item allows you to control the DRAM speed.
The choice: Host Clock, HCLK-33M, HCLK+33M.
SDRAM Cycle Length
This field sets the CAS latency timing.
The choices: 3, 2.
Summary of Contents for PCM-6894
Page 10: ...Appendix A WatchDog Timer 81 Appendix B Optional Extras 89...
Page 18: ...PCM 6894 8 PCM 6894 User ManualBC 599 596 Locating Jumpers Connectors...
Page 19: ...Chapter 2 Installation 9 Locating Jumpers Connectors...
Page 20: ...PCM 6894 1 0 PCM 6894 User ManualBC 599 596 Mechanical Drawing...
Page 21: ...Chapter 2 Installation 11 Mechanical Drawing...
Page 82: ...72 PCM 6894 User Manual...
Page 91: ...Appendix A Watchdog Timer 81 Watchdog Timer A P P E N D I X...
Page 98: ...88 PCM 6894 User s Manual...
Page 99: ...Appendix B Optional Extras 89 Optional Extras A P P E N D I X...