6220M Mainboard Chapter 3 Award BIOS Setup
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CHIPSET FEATURES SETUP
This screen controls the setting for the chipset
on the mainboard.
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
SDRAM CAS Latency Time
: 3
Auto Detect DIMM/PCI ClK
: Disabled
DRAM Data Integrity Mode
: Non-ECC Spread Spectrum Modulated
: Disabled
System BIOS Cacheable
: Disabled Software Clock Control
: Disabled
Video BIOS Cacheable
: Disabled CPU Clock Frequency
: 66MHz
Video RAM Cacheable
: Disabled *
Following menus are
Optional*
8-bit I/O Recovery Time
: 3
*CPU Warning Temperature
: Disabled
16-bit I/O Recovery Time
: 2
*Current System Temp.
: 20
o
C/ 68
o
F
Memory Hole At 15M-16M
: Disabled *Current CPU Temperature
: 20
o
C/ 68
o
F
Passive Release
: Enabled
*Current CHASSISFAN Speed : 0 PRM
Delayed Transaction
: Disabled *Current PWRFAN Speed
: 0 PRM
AGP Aperture Size (MB)
: 128
*Current CPUFAN Speed
: 0 PRM
AGP/PCI MultiDisplay
: Disabled *Vcore : 2.80V VTT(V) : 2.81V
Following items for EDO DRAM Only
*+3.3V : 3.45V +5V
: 4.91V
EDO Auto Configuration
: Enabled
*+12V : 12.22V –12V
: -11.76
EDO DRAM Speed Selection
: 60ns
*-5V : -5.16V
EDO CASx# MA Wait State
: 2
Esc: Quit
→
: Select Item
EDO RASx# Wait State
: 1
F1 : Help
PU/PD/+/-: Modify
F5 : Old Values
(Shift)F2
: Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
SDRAM CAS Latency Time
You could select CAS latency time in HCLKS of 2/2
or 3/3. The system board designer should set the values in this field, depending on the
DRAM installed. Do not change the values in this field unless you change
specifications of the installed DRAM or the installed CPU. The choice : 2, 3.
DRAM Data Integrity Mode
Select parity, ECC, or Disabled, depending on the type
of DRAM installed in your system. The choice : ECC, Parity, Disabled.
System BIOS Cacheable
Selecting Enabled allows the caching of the system BIOS
ROM at F0000h-FFFFFh, resulting in better system performance. However, if any
program writes to this memory area, a system error may result.
