Zida TX694X, Руководство пользователя

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BIOS
Setup
Page 23 Mainboard User's Manual
Advanced Chipset Features
DRAM Timing By SPD
This item controls the DRAM timing, it allows you to enable/disable the
DRAM timing by SPD. The choices : Enabled, Disabled.
DRAM Clock
This item allows you to control the DRAM speed.
The choices: Host CLK, HCLK-33M.
SDRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field from
the default value specified by the system designer.
The choices: 2, 3.
Bank Interleave
This item allows you to control the bank interleave. The choices:
Disabled, 2 bank, 4 bank.
DRAM Drive Strength
This item allows you to auto / manual the DRAM Drive Strength.
The choices : auto, manual.