Mainboard User's Manual
Page 28
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero wait states.
The choices: Enabled, Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1. The choices: Enabled, Disabled.
PCI#2 Access #1 Retry
When Disabled, PCI#2 will not be disconnected until access finishes
(default). When enabled, PCI#2 will be disconnected retries are
attempted without success. The choices: Enabled, Disabled.
AGP Master 1 WS Write
When Enabled, writes to the AGP(Accelerated Graphics Port) are
executed with one wait states. The choices: Enabled, Disabled.
AGP Master 1 WS Read
When Enabled, read to the AGP(Accelerated Graphics Port) are
executed with one wait states. The choices: Enabled, Disabled.
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