© Copyright 2013 Zephyr Engineering, Inc
UDPSDR-
HF2 User’s Manual
3
Version 3.5
– 3 October 2013
Figure 3 - Power Connector Detail
1.1.1.3 J4
– Reference Clock Input (optional)
J4 can be used as an optional reference clock input. You may apply a 2V peak-to-peak
10MHz sine-wave input from a GPS-disciplined oscillator to this standard SMA jack.
This signal is squared and applied to an FPGA input. FPGA code can phase-lock the
on-board 122.88MHz VCXO sampling clock to this signal for precise frequency control
of the ADC sampling clock.
Note
: The current FPGA code implementations do not use the J4 input. It is available as
an option for the user.
1.1.1.4 J5
– RF Input
The receiver RF input is connected to J5, a standard SMA jack. J5 may be connected
directly to a 50-ohm antenna or to the receive port of the UDPSDR-TX2 transmitter.
1.1.1.5 J6
– Phones Out (optional)
Plug headphones into J6, a 3.5mm stereo jack, which connects to the on-board
CODEC/headphone amplifier.
Note
: The current FPGA code implementations send receive audio to the PC sound
system rather than to J6. It is available as an option for the user.
1.1.2 UDPSDR-HF2 Headers and Jumpers
1.1.2.1 JP1
– TERM Header
Placing a 2mm jumper on JP1 pins 2-3 adds a 50-ohm termination to the
Reference
Clock Input
from J4. JP1 pin 1 is connected to system ground for use while probing the
J4 input signal on pin 2. Placing a jumper on JP1 pins 1-2 will place an AC ground
across the J4 input, and is not recommended while driving a signal into J4. (Factory
default is no jumper installed.)
+5VDC - Pin 1
GND - Pin 2
Center Pin +5VDC@950mA
2.35mm x 0.70mm
