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© Copyright 2013 Zephyr Engineering, Inc

UDPSDR-

HF2 User’s Manual

5

Version 3.5

– 3 October 2013

1.2.1.1 USB Connector (X201)

The USB connector is used to program both the FPGA configuration RAM and the
BeMicroSDK configuration flash memory. The BeMicroSDK appears to the host PC as
an Altera Byte Blaster.

The USB connector can also be used to power the SDRstick

TM

HF2 when it is

connected to a port that can supply sufficient power. USB 3.0 ports and some USB 2.0
powered hubs can power this 950mA load, however it is highly recommended to use a
5V well regulated power supply on J3 (or P1) rather than the SDRstick

TM

USB

connector.

WARNING: NEVER APPLY EXTERNAL POWER TO J3/P1 WHILE PLUGGED INTO
ANY USB PORT! THIS CAN DAMAGE YOUR USB PORT!

Note

: In order to get the SDRstick

TM

HF2 to power up from a Windows PC USB port, the

Altera Byte Blaster driver must be installed. A Byte Blaster driver is not needed for PCs
running Linux in order to power up the SDRstick

TM

HF2.

1.2.1.2 Ethernet Connector (X602)

The Ethernet connector (X602) is a standard RJ-45 connector. The BeMicroSDK
supports 10/100Mbps Ethernet, but 100Mbps is required for SDRstick

TM

HF2. This

connection is used for the receive data stream to a host PC or network switch.

1.2.1.3 MEC Edge connector (X701)

The 80-contact MEC-style edge connector plugs into the UDPSDR-HF2 front-end
board. All of the digital signals between the HF2 and the BeMicroSDK use this
connector. Pin 1 is clearly marked on both the BeMicroSDK and the HF2 board.

Note

: The pin numbering is different than that shown on the Samtec connector data

sheet. Be sure to only plug the boards together in one of the two configurations shown
in Figure 2.

1.2.2 BeMicroSDK LEDs

There are two groups of LEDs on the BeMicroSDK: a group of 3 status LEDs below the
RJ-45 connector and a group of 8 user LEDs alongside the MEC connector.

1.2.2.1 Status LEDs (V701, V703, V704)

The leftmost status LED (V701) is the green power indicator LED. The middle status
LED (V703) is yellow, and is lit when the FPGA CONF_DONE pin goes high. The
rightmost status LED (V704) is red and lights when pin 4 of the MEC connector is pulled
low (PWREN2# asserted). Since HF2 never drives this pin low, this LED should never
be lit. See Figure 5 for the status LED locations.

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Содержание UDPSDR-HF2

Страница 1: ...UDPSDR HF2 Receiver Front end User s Manual Version 3 5 3 October 2013 Copyright 2013 Zephyr Engineering Inc ...

Страница 2: ...13 3 3 1 SIDEBAR BEMICROSDK CONFIGURATION FLASH ROM AND THE UFB 13 3 3 2 QS3A CREATING A USER FLASH BLOCK FILE 14 3 3 3 QS3B PROGRAMMING THE BEMICROSDK CONFIGURATION FLASH ROM 14 3 3 4 SIDEBAR HOW THE BEMICROSDK GETS ITS MAC AND IP ADDRESSES 14 3 4 STEP QS4 MAKE EXTERNAL CONNECTIONS 15 3 4 1 QS4B ANTENNA 15 3 4 2 QS4C ETHERNET DATA CONNECTION 15 3 4 3 QS4D POWER 15 3 5 STEP QS5 INSTALL AND RUN GUI...

Страница 3: ... 1 UDPSDR HF2 Topside Connectors and Jumpers 1 1 1 UDPSDR HF2 Connectors 1 1 1 1 J1 and J2 BeMicroSDK connector The J1 and J2 80 pin dual sided MEC style edge connectors plug onto the gold finger edge connector on the end of the BeMicroSDK Either J1 or J2 connect digital data and power between the HF2 and the BeMicroSDK Either connector may be used all J1 and J2 pins are connected in parallel J3 P...

Страница 4: ...RstickTM HF2 requires 5VDC at about 950mA J3 and P1 are equivalent since they are in parallel J3 mates with a 2 35mm x 0 7mm barrel plug CUI part PP 012 Digi Key part CP 012 ND P1 is provided for either a two pin SMT header TE part 3 647166 2 Digi Key part A113590 ND or just pads for soldering wire leads The center pin of J3 is positive P1 pin 1 is positive and is marked with a white dot adjacent ...

Страница 5: ...d to J5 a standard SMA jack J5 may be connected directly to a 50 ohm antenna or to the receive port of the UDPSDR TX2 transmitter 1 1 1 5 J6 Phones Out optional Plug headphones into J6 a 3 5mm stereo jack which connects to the on board CODEC headphone amplifier Note The current FPGA code implementations send receive audio to the PC sound system rather than to J6 It is available as an option for th...

Страница 6: ...tomization options Headers P3 and P4 are available as a user option See Table 1 for P3 and P4 pin connections P3 P4 pin number P3 function P4 function 1 3 3V 3 3V 2 3 3V 3 3V 3 on board FL1 LPF input RF to LNA input 4 RF from attenuator output on board FL1 LPF output 5 GND GND 6 GND GND Table 1 P3 and P4 Header Pin Connections 1 2 BeMicroSDK Connectors Switches and LEDs See Figure 4 for BeMicroSDK...

Страница 7: ... is a standard RJ 45 connector The BeMicroSDK supports 10 100Mbps Ethernet but 100Mbps is required for SDRstickTM HF2 This connection is used for the receive data stream to a host PC or network switch 1 2 1 3 MEC Edge connector X701 The 80 contact MEC style edge connector plugs into the UDPSDR HF2 front end board All of the digital signals between the HF2 and the BeMicroSDK use this connector Pin ...

Страница 8: ...ed meaning Some of the user LEDs are used to indicate some common conditions by the SDRstickTM firmware shown in Table 2 See Figure 6 for user LED locations LED Function LED8 top lit on A D converter overload condition LED7 lit on FIFO overflow internal error condition LED6 off LED5 off LED4 off LED3 off LED2 Heartbeat flashes 1Hz from HF2 122 88MHz clock LED1 bottom Heartbeat flashes 1Hz from BeM...

Страница 9: ... switch is pressed the FPGA is reloaded from the on board flash memory and restarts in the same manner as a power on reset The middle push button switch S503 labeled Reset is used to reset the FPGA logic and internal soft core CPU Note that this does not cause a reconfiguration it merely restarts the FPGA logic from a known reset state The top push button switch S504 labeled User can be read by th...

Страница 10: ...Figure 7 BeMicroSDK Switches 1 2 3 2 Slide Switches SW1 1 SW1 2 The two slide switches SW1 1 bottom and SW1 2 top can be read under FPGA firmware control SW1 1 and SW1 2 are not currently used by the FPGA firmware SW1 1 not used SW1 2 not used S502 Reconfiguration S503 FPGA Reset S504 not used ...

Страница 11: ...icroSDK flash memory QS4 Make external connections a Remove BeMicroSDK from computer b Install HF2 onto BeMicroSDK and connect antenna to J5 c Connect Ethernet cable to host PC or network d Connect power and observe two flashing heartbeat LEDs on BeMicroSDK QS5 Install and Run GUI software on computer a One or more of GNURadio HDSDR SDR PowerSDRTM are options b ExtIO_SDRSTICK dll must be placed in...

Страница 12: ...into FPGA configuration SRAM Quartus II Programmer 140MB Altera com Program FPGA firmware into FPGA configuration SRAM USB Blaster Driver Included in Quartus II Web Edition and Quartus II Programmer Enable BeMicroSDK USB power Windows required to program FPGA configuration SRAM or BeMicroSDK configuration flash memory SDRstick TM Programmer 750KB svn SDRstick com Program BeMicroSDK configuration f...

Страница 13: ...er If your BeMicroSDK came pre loaded from the factory and you are powering it from external power you do not need to install any support software If at some point you want to upgrade the firmware you will need to install the necessary components from Table 4 You can do this at any time as you need them To Do This You Need This Support Software Power HF2 from external power none Power HF2 from USB...

Страница 14: ...ware 3 1 2 3 USB Blaster Driver No download of the USB Blaster driver is required as it is included with both the Quartus II Web Edition and Quartus II Programmer 3 1 2 4 SDRstickTM Programmer SDRstickTM Programmer is a Windows application that you can download from svn sdrstick com Look in the sdrstick release directory under sdrstick programmer The SDRstickTM Programmer from svn sdrstick com is ...

Страница 15: ...n flash ROM on the BeMicroSDK 3 3 1 SideBar BeMicroSDK Configuration flash ROM and the UFB The BeMicroSDK flash ROM is divided up into three sections FPGA fabric NIOS soft core CPU program code and the User Flash Block UFB Each of these sections is programmed from a FLASH format file Two of these files provide the functionality of the FPGA and are supplied by the factory The third file defines the...

Страница 16: ...lled on the PC 3 3 3 QS3b Programming the BeMicroSDK Configuration Flash ROM Use the Program Flash pane to program FPGA firmware FLASH files and UFB FLASH file into the BeMicroSDK configuration flash ROM Click the Add button to add files to the Files to Program window Files can be added in any order A section of the ROM will only be programmed if the corresponding FLASH file appears in this window...

Страница 17: ...d If the DHCP request is unsuccessful for example a timeout occurs the SDRstickTM uses the default IP address of 192 168 1 25 3 4 Step QS4 Make External Connections The SDRstickTM requires three external connections to function antenna Ethernet data connection and power input 3 4 1 QS4b Antenna Connect an antenna to the J5 SMA connector Note that there is no bandpass filtering at the receiver fron...

Страница 18: ...gh Definition Software Defined Radio or HDSDR is a freeware SDR program for Windows 2000 through Windows 8 HDSDR is written by Mario Taeubel DG0JBJ and is an advanced version of Winrad This is an excellent SDR GUI and may be downloaded from the HDSDR web site http www hdsdr de The HDSDR download is an executable installer for Windows Simply download it to a directory on your local drive and run it...

Страница 19: ...15Mbps which may be transportable over most 802 11g or 802 11n WiFi networks but not over 802 11b networks 3 5 1 1 3 Front End Attenuator The 31 dB front end step attenuator is controlled by the RF 0 button in the upper right of the cluster of blue button located above the date display Click on this button and a slider will pop up next to the RF 0 button As you move the slider down notice that the...

Страница 20: ...s Priority Under the Audio Primary tab select 384000 in the Sample Rate box Under the Audio VAC1 tab click the Enable VAC 1 check box Close the Setup window and click the Power button and you are on the air If you go back to the Setup window now under the General Hardware Config tab you will see your SDRstickTM IP and MAC addresses displayed in the lower right corner of the window under Hermes Add...

Страница 21: ...r reading through this chapter please log onto the SDRstickTM Yahoo group and ask for help To subscribe to the group go to http groups yahoo com groups SDRstick 4 1 PATH variable incorrectly set Symptom SDRstickTM Programmer appears to run but the several windows just momentarily flash up on the screen and the BeMicroSDK does not get programmed Cause SDRstickTM Programmer cannot find the software ...

Страница 22: ...es on the entire network are unique and that all IP address bits with a 1 in the network mask are the same For example if your PC is set to IP address 192 169 1 10 with a net mask of 255 255 255 0 then you can set your SDRstickTM IP address to 192 168 1 xx where xx a number from 1 to 254 excluding 10 which is already used by your PC 4 5 ExtIO dll not in correct directory Symptom HDSDR and or SDR s...

Страница 23: ...RO_PWR 5V RIGHT LEFT SMA SMA EXT_OSC 8 Figure 10 UDPSDR HF2 Hardware Block Diagram 5 2 UPDSDR HF2 FPGA Code The UDPSDR HF2 simplified FPGA block diagram is shown in Figure 11 This very basic flow shows the Numerically Controlled Oscillator and the two multipliers that serve as a down converter followed by two decimating filters The I Q data is buffered by a FIFO and sent to the Ethernet MAC for tr...

Страница 24: ...ency Range 100kHz to 55MHz Digital Direct Sampling DDS Input impedance 50 ohms RF input clipping level typical attenuator off 10dBm RF input clipping level typical attenuator at 31dB 21dBm Maximum Display Bandwidth 1 92MHz Sampling Width and Rate 16bits 122 88Msps MDS 128dBm 14MHz 500Hz BW for 3dB noise floor increase Antenna connection standard SMA Power consumption 5VDC 950mA including BeMicroSD...

Страница 25: ...6 n c 17 INA4 18 n c 19 INA5 20 n c 21 GND 22 GND 23 INA6 24 n c 25 INA7 26 n c 27 INA8 28 n c 29 INA9 30 n c 31 INA10 32 GND 33 GND 34 n c 35 INA11 36 n c 37 INA12 38 n c 39 INA13 40 n c 41 INA14 42 n c 43 INA15 44 GND 45 n c 46 n c 47 RAND 48 n c 49 OVFLA 50 n c 51 PGA 52 CMCLK 53 GND 54 GND 55 CDIN 56 DITHER 57 n c 58 n c 59 CBCLK 60 PH_CODEC_nCS 61 CLRCIN 62 SPI_DATA 63 CLRCOUT 64 SPI_CLK 65 V...

Страница 26: ...TC2208 PGA programmable gain amp control input pin CMCLK TLV320AIC23B XTI MCLK input pin CDIN TLV320AIC23B DIN input pin DITHER LTC2208 DITHER dither control input pin CBCLK TLV320AIC23B BCLK input pin PH_CODEC_nCS TLV320AIC23B CSn input pin CLRCIN TLV320AIC23B LRCIN input pin SPI_DATA DAT 31 SP data input pin and TLV320AIC23B SDIN input pin CLRCOUT TLV320AIC23B LRCOUT input pin SPI_CLK DAT 31 SP ...

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