YSI 5000, Руководство по обслуживанию

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YSI Incorporated Model 5000/5100 Service Manual 27
start or stop bit. When the master has finish communication the chip select is brought LOW
ending the transfer.
REAL TIME CLOCK, U24
The real time clock shares the serial bus with other peripherals, it is device 2 (uses serial cs2).
The RTC chip select line is inverted to make it compatible with the bus. The RTC includes a
256 bit scratch pad ram and a 4096 bit SRAM all of which are powered from an on board lithium
cell, B1, for non-volatile operation.
87C750 PERIPHERAL HARDWARE
The 87C750 scans the keypad, monitors the power switch and low battery signal, monitors the
bar code wand and drives the buzzer. The peripheral communicates events to the master though
a serial bus.
A maximum of 20 keys can be scanned in a matrix. Five normally high row inputs must be
connected to port pins P3.3, P3.4, P3.5, P3.6 and P3.7. If a row is not used it will still be scanned
so must be left unconnected or tied high. Four column drive lines connect to P1.0, P1.1, P1.2
and P1.3. Columns are pulled low when scanned and should are left unconnected if unused.
The signals at P3.1 and P3.2 are sampled and reported in the status byte every 1/40th of a second.
If P3.2 is high a bit is set in the status register until the register is read. The level on P3.1 is
polled every 1/40th of a second and passed directly to a bit in the status register. P3.1 will be
used for the low battery signal and P3.2 for the power switch.
A piezo buzzer may be connected to U19 pin 6, driven by port pin P3. A buzz of variable length
can then be initiated by a command from the master.
The bar code wand or PC AT style keyboard connects to P1.6 and P1.7. The clock line on P1.6
so on interrupt is generated for each data bit.
P1.4 is an interrupt output. Any time status changes, keys are pressed or a bar code character
comes in , P1.4 is brought low. It is held low until the status register is read.
P1.5, an external interrupt is used for the master serial line and P0.1 for the data. The chip is
selected by brining P0.0 high. See below for interface and timing details.
RS232 PORT
The port is driven by U18 (LTC1384) which implements TXD,RXD,DSR and DTR. The logic
signals are isolated by opto couplers U14 and U15. The five volt supply is also isolated by
CLOCK
DATA Pin
(Master) High
DATA Pin
(Slave)
High
Read Command and Return