6.9 Counter - In-/output area
n
By including the SPEEDBUS.GSD in your hardware configurator, the module is at
your disposal in the hardware catalog. After the installation of the GSD you will find
the CPU at
‘Additional field devices
è
I/O
è
VIPA_SpeedBus’
. 314-6CF23.
n
If there is no hardware configuration available, the in- and output areas starting with
address 1024 are mapped to the address range of the CPU.
n
For each input bit the status is stored in the data input area.
n
For the output you have to enter a value into the data output are.
Used area
Addr.
Name
Byte
Function
+0
DI_0
1
Digital input I+0.0 ... I+0.7
+1
DI_1
1
Digital input I+1.0 ... I+1.7
+16
CVCL_0
4
Counter value / latch value counter 0
+20
-
2
reserved
+22
ISTS_0
2
Input status counter 0
+24
CVCL_1
4
Counter value / latch value counter 1
+28
-
2
reserved
+30
ISTS_1
2
Input status counter 1
+32
CVCL_2
4
Counter value / latch value counter 2
+36
-
2
reserved
+38
ISTS_2
2
Input status counter 2
+40
CVCL_3
4
Counter value / latch value counter 3
+44
-
2
reserved
+46
ISTS_3
2
Input status counter 3
Used area
Addr.
Name
Byte
Function
+0
-
1
reserved
+1
DO_1
1
Digital output Q+1.0 ... Q+1.7
+10
OSTS_0
2
Output status counter 0
+12
-
2
reserved
+14
OSTS_1
2
Output status counter 1
+16
-
2
reserved
+18
OSTS_2
2
Output status counter 2
+20
-
2
reserved
+22
OSTS_3
2
Output status counter 3
The
counter value
always contains the current value of the counter.
Access to the digital part
Counter value counter
X
VIPA System 300S
+
Deployment I/O periphery
Counter - In-/output area
HB140 | CPU | 314-6CF23 | en | 19-01
112