YDP-323
15
■
LSI PIN DESCRIPTION
HD6433690FYV H8/300 (X6008100) CPU (E-HOSTs)
PIN
NO.
NAME
I/O
FUNCTION
PIN
NO.
NAME
I/O
FUNCTION
Analog Power Supply (+3.3V)
(Pull Up)
Sub Clock Output
- (NC)
Sub Clock Input
- (NC)
Internal Power Supply (+3.3V)
- (NC)
RESET input
- (NC)
TEST input
- (NC)
Ground
(Pull Up or Vcc)
Clock output
- (NC)
Clock input
- (NC)
Power supply
SCK3 (Main CPU)
- (NC)
RXD (Pull Up)
- (NC)
TXD (Main CPU)
Active Sensing ON/OFF
/IRQ0 (Main CPU)
- (NC)
- (NC)
- (NC)
- (NC)
- (NC)
- (NC)
- (NC)
Analog Controller (AN4)
- (NC)
Analog Controller (AN5)
/E-IC
Analog Controller (AN6)
SDA
Analog Controller (AN7)
SCL
Analog Controller (AN3)
- (NC)
Analog Controller (AN2)
- (NC)
Analog Controller (AN1)
- (NC)
Analog Controller (AN0)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
-
O
I
-
I
I
-
O
I
-
O
O
I
O
O
O
O
O
O
I/O
I/O
O
O
O
Avcc
X2
X1
Vcl
/RES
TEST
Vss
OSC2
OSC1
Vcc
P50
P51
P52
P53
P54
P55
P10
P11
P12
P56
P57
P74
P75
P76
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
/NMI
P80
P81
P82
P83
P84
P85
P86
P87
P20
P21
P22
P14
P15
P16
P17
P84
P85
P86
P87
P83
P82
P81
P80
I
O
O
O
O
O
I
O
O
O
I
O
I
O
O
O
I
I
I
I
I
I
I
I
PIN
NO.
I/O
FUNCTION
NAME
PIN
NO.
I/O
FUNCTION
NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
Vss0
V
DD
0
P30
P31
P32/SDA0
P33/SCL0
P34
P35
P36
P20/SI30
P21/SO30
P22/SCK30
P23RxD0
P24/TxD0
P25/ASCK0
V
DD
1
AVss
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I
I
I
I
I
I
I
Port 5 / Higher address bus
Ground
Power supply
Port 3
Port 3 / Serial data input/output
Port 3 / Serial clock input/output
Port 3
Port 2 / Serial data input
Port 2 / Serial data output
Port 2 / Serial clock input/output
Port 2 / Serial data input
Port 2 / Serial data output
Port 2 / Serial clock input/output
Power supply
Ground
Port 1 / A/D converter analog input
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P10/ANI0
AV
REF
AV
DD
RESET
XT2
XT1
IC
X2
X1
Vss1
P00/INTP0
P01/INTP1
P02/INTP2
P03/INTP3/ADTRG
P70/TI00/TO0
P71/TI01
P72/TI50/TO50
P73/TI51/TO51
P74/PCL
P75/BUZ
P64/RD
P65/WR
P66/WAIT
P67/ASTB
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
A47/AD7
I
I
-
I
-
I
-
-
I
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 1 / A/D converter analog input
A/D converter reference voltage input
Analog power supply
System reset input
Subsystem clock oscillation
Internally connected
Main system clock oscillation
Ground
Port 0 / External interrupt request input
Port 0 / External interrupt request input / Trigger signai input
Port 7 / External count clock input / 16-bit timer/event counter 0 output
Port 7 / Capture trigger input
Port 7 / External count clock input / 8-bit timer/event counter 50 output
Port 7 / External count clock input / 8-bit timer/event counter 51 output
Port 7 / Clock output
Port 7 / Buzzer output
Port 6 / Strobe signal output for reading
Port 6 / Strobe signal output for writing
Port 6 / Wait insertion
Port 6 / Strobe output
Port 4 / Lower address/data bus
µ
PD780031AYGK-NO4 (X0031200) LKS
