Yamaha Tyros4, Руководство по обслуживанию

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37
Tyros4
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VCC3A3
GND3A3
TPI+
TPI
VCC18A
TPO+
TPO-
GND18A
V18F
VCC3R3
GND3R3
TEST2
TEST1
I_LK/ACT
I_SPEED
I_FULL/COL
RSTn
GND
EEDIO
EECK
EECS
PME
IRQ
VCCK
VCC3IO
GND
SD15
SD14
SD13
SD12
SD11
SD10
I
I
O
O
I
I
O
O
O
I
I/O
I/O
I/O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
Power supply for analog circuit (+3.3V DC)
Power supply for analog circuit (+0V DC or Ground power)
Twisted pair receive input, positive
Twisted pair receive input, negative
Analog power for oscillator, PLL, and Ethernet
PHY differential I/O pins, 1.8V
Twisted pair transmit output, positive
Twisted pair transmit output, negative
Analog ground for oscillator, PLL, and Ethernet
PHY differential I/O pins
On-chip 3.3V to 1.8V Regulator 1.8V DC
On-chip 3.3V to 1.8V Regulator power supply (+3.3V DC)
On-chip 3.3V to 1.8V Regulator ground
TEST mode select
Link status/Active
Speed status
Full-duplex/Collision status
Reset
Ground
EEPROM data in/out
EEPROM clock
EEPROM chip select
Wakeup indicator
Programmable interrupt request
Power supply for core logic (+1.8V DC)
Power supply for IO (+3.3V DC)
Ground
System data bus
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
VCCK
VCC3IO
SA5,FIFO_SEL
SA4
SA3
SA2
SA1
SA0
AEN,PSEN
CSn
RDn
WRn
IOIS16n
TCLK
TClK_EN
GND
VCCK
VCC18A
XTALIN
XTALOUT
GND18A
RSET_BG
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I/O
I
I
I
O
O
System data bus
Power supply for core logic (+1.8V DC)
Power supply for IO (+3.3V DC)
System address or FIFO select
System address
Address enable
Chip select
Read
Write
16 bit port
Test Clock Pin
Enable TCLK in to ASIC as a main clock for test only
Ground
Power supply for core logic (+1.8V DC)
Analog power for oscillator, PLL, and Ethernet
PHY differential I/O pins, 1.8V
Crystal/Oscillator input
Crystal/Oscillator output
Analog ground for oscillator, PLL, and Ethernet
PHY differential I/O pins
Off-chip resister
DM: IC400
AX88796BLF
(YC258A00)
LAN CONTROLLER
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TxIn4
V
CC
TxIn5
TxIn6
GND
TxIn7
TxIn8
V
CC
TxIn9
TxIn10
GND
TxIn11
TxIn12
V
CC
TxIn13
TxIn14
GND
TxIn15
TxIn16
TxIn17
V
CC
TxIn18
TxIn19
GND
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I LVTTL level input
Power supply pin for LVTTL inputs
LVTTL level input
Ground pin for LVTTL inputs
LVTTL level input
Power supply pin for LVTTL inputs
LVTTL level input
Ground pin for LVTTL inputs
LVTTL level input
Power supply pin for LVTTL inputs
LVTTL level input
Ground pin for LVTTL inputs
LVTTL level input
Power supply pin for LVTTL inputs
LVTTL level input
Ground pin for LVTTL inputs
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 TxIn20
TxCLKIn
PwrDn
PLL GND
PLL V
CC
PLL GND
LVDS GND
T
TxCLKOut-
TxOut2-
LVDS GND
LVDS V
CC
TxOut1-
TxOut0-
LVDS GND
N.C.
TxIn0
TxIn1
GND
TxIn2
TxIn3
I
I
I
I
I
I
I
O
O
O
O
I
I
O
O
O
O
I
I
I
I
I
I
LVTTL level input
LVTTL level clock input
LVTTL level power-down input
Ground pin for PLL
Power supply pin for PLL
Ground pin for PLL
Ground pin for LVDS outputs
Positive LVDS differential clock output
Negative LVDS differential clock output
Positive LVDS differential data output
Negative LVDS differential data output
Ground pin for LVDS outputs
Power supply pin for LVDS outputs
Positive LVDS differential data output
Negative LVDS differential data output
Positive LVDS differential data output
Negative LVDS differential data output
Ground pin for LVDS outputs
Not connected
LVTTL level input
Ground pin for LVTTL inputs
LVTTL level input
FIN1215MTDX
(YC491A00)
LVDS SERIALIZER/DE-SERIALIZER
IC014
IC014
DM: IC304