43
Tyros3
PIN
NO.
I/O
FUNCTION
NAME
PIN
NO.
I/O
FUNCTION
NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P50/A8
P51/A9
P51/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
Vss0
V
DD
0
P30
P31
P32/SDA0
P33/SCL0
P34
P35
P36
P20/SI30
P21/SO30
P22/SCK30
P23/RxD0
P24/TxD0
P25/ASCK0
V
DD
1
AVss
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I
I
I
I
I
I
I
Port 5 / Higher address bus
Ground
Power 5 V
Port 3
Port 3 / Serial data input/output
Port 3 / Serial clock input/output
Port 3
Port 2 / Serial data input
Port 2 / Serial data output
Port 2 / Serial clock input/output
Port 2 / Serial data input
Port 2 / Serial data output
Port 2 / Serial clock input/output
Power 5 V
Ground
Port 1 / A/D converter analog input
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P10/ANI0
AV
REF
AV
DD
RESET
XT2
XT1
IC
X2
X1
Vss1
P00/INTP0
P01/INTP1
P02/INTP2
P03/INTP3/ADTRG
P70/TI00/TO0
P71/TI01
P72/TI50/TO50
P73/TI51/TO51
P74/PCL
P75/BUZ
P64/RD
P65/WR
P66/WAIT
P67/ASTB
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
A47/AD7
I
I
-
I
-
I
-
-
I
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 1 / A/D converter analog input
A/D converter reference voltage input
Analog power 5 V
System reset input
Subsystem clock oscillation
Internally connected
Main system clock oscillation
Ground
Port 0 / External interrupt request input
Port 0 / External interrupt request input / Trigger signai input
Port 7 / External count clock input / 16-bit timer/event counter 0 output
Port 7 / Capture trigger input
Port 7 / External count clock input / 8-bit timer/event counter 50 output
Port 7 / External count clock input / 8-bit timer/event counter 51 output
Port 7 / Clock output
Port 7 / Buzzer output
Port 6 / Strobe signal output for reading
Port 6 / Strobe signal output for writing
Port 6 / Wait insertion
Port 6 / Strobe output
Port 4 / Lower address/data bus
μ
PD780031AYGK-N09
(XZ916300)
E-PNS2a LED/SWITCH DRIVER
PIN
NO.
I/O
FUNCTION
NAME
PIN
NO.
I/O
FUNCTION
NAME
DS99R104TSQX/NOPB
(X9324A00)
LVDS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
RPWDNB
RESRVD
ROUT[23:16]
ROUT[23:16]
ROUT[23:16]
ROUT[23:16]
V
DD
OR3
VssOR3
ROUT[23:16]
ROUT[23:16]
ROUT[23:16]
ROUT[23:16]
ROUT[15:8]
ROUT[15:8]
ROUT[15:8]
ROUT[15:8]
LOCK
RCLK
VssOR2
V
DD
OR2
ROUT[15:8]
ROUT[15:8]
ROUT[15:8]
ROUT[15:8]
ROUT[7:0]
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Receiver Data Enable
●
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
●
REN = L; ROUT[23-0] and RCLK are Disabled (OFF),
Receiver ROUT[23-0] and RCLK Outputs are in TRI-
STATE, PLL still operational and locked to TCLK.
RESERVED - This pin MUST be tied LOW.
LVDS SERIAL INTERFACE PINS
Receiver Parallel Interface Data Outputs _ Group 3
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
Receiver Parallel Interface Data Outputs _ Group 3
Receiver Parallel Interface Data Outputs - Group 2
LOCK indicates the status of the receiver PLL
●
LOCK = H; receiver PLL is locked
●
LOCK = L; receiver PLL is unlocked,
ROUT[23-0] and RCLK are TRI-STATED
Parallel Interface Clock Output Pin.
Strobe edge set by RRFB configuration pin.
Digital Ground, LVCMOS Output Ground
Digital Voltage supply, LVCMOS Output Power
Receiver Parallel Interface Data Outputs - Group 2
Receiver Parallel Interface Data Outputs - Group 1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
ROUT[7:0]
ROUT[7:0]
ROUT[7:0]
VssOR1
V
DD
OR1
ROUT[7:0]
ROUT[7:0]
ROUT[7:0]
ROUT[7:0]
VssR0
V
DD
R0
V
DD
R1
VssR1
V
DD
IR
VssIR
RIN+
RIN-
RRFB
VssPR1
V
DD
PR1
VssPR0
V
DD
PR0
REN
O
O
O
O
O
O
O
O
O
I
I
I
I
Receiver Parallel Interface Data Outputs - Group 1
Digital Ground, LVCMOS Output Ground
Digital Voltage supply, LVCMOS Output Power
Receiver Parallel Interface Data Outputs - Group 1
Digital Ground, Logic Ground
Digital Voltage supply, Logic Power
Digital Voltage supply, Logic Power
Digital Ground, Logic Ground
Analog LVDS Voltage supply, Power
Analog LVDS Ground
Receiver LVDS True (+) Input
This input is intended to be terminated with a
100 ohm load to the RIN+ pin.
Receiver LVDS Inverted (-) Input
This input is intended to be terminated with a
100 ohm load to the RIN- pin.
Receiver Clock Edge Select Pin
●
RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge.
●
RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.
Analog Ground, PLL VCO Ground
Analog Voltage supply, PLL VCO Power
Analog Ground, PLL Ground
Analog Voltage supply, PLL Power
Receiver Data Enable
●
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
●
REN = L; ROUT[23-0] and RCLK are Disabled (OFF),
Receiver ROUT[23-0] and RCLK Outputs are in TRI-
STATE, PLL still operational and locked to TCLK.
Содержание Tyros3
Страница 50: ...50 Tyros3 DM Circuit Board 2NA WM15450 C C to AJK CN7 to AJK CN1 to LCR CN202 to PNR CN4 N C ...
Страница 53: ...53 Tyros3 D D DIMM 168 pin Pattern side Scale 90 100 2NA WM15450 ...
Страница 60: ...60 Tyros3 PNC Circuit Board H H G G 1 up down 2 3 4 5 6 7 2NA WM24260 ...
Страница 62: ...62 Tyros3 PNR Circuit Board I I to PNL CN4 to DM CN205 2NA WM24240 ...
Страница 63: ...63 Tyros3 Component side 2NA WM24240 I I ...
Страница 64: ...64 Tyros3 PNR Circuit Board J J 2NA WM24240 ...
Страница 65: ...65 Tyros3 Pattern side 2NA WM24240 J J to PNC CN2 ...
Страница 68: ...68 Tyros3 PNL Circuit Board K K 2NA WM24250 ...
Страница 69: ...69 Tyros3 Scale 85 100 Component side K K to PNR CN2 2NA WM24250 ...
Страница 70: ...70 Tyros3 PNL Circuit Board L L to LCL CN5 to SWITCHING POWER SUPPLY CN5 2NA WM24250 ...
Страница 71: ...71 Tyros3 Scale 85 100 Pattern side 2NA WM24250 L L to PNLS CN202 to PITCHBEND to MODULATION ...
Страница 76: ...76 Tyros3 MK61L Circuit Board Component side O O N C O O P P P P to MKH D CN4 2NAKZ WD80020 3 ...
Страница 77: ...77 Tyros3 MK61L Circuit Board Pattern side Q Q 2NAKZ WD80020 3 Q Q R R R R ...
