Yamaha PM 5000 Series, Руководство по обслуживанию

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99
PM5000
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D5
D6
D7
/IRQ0
/IRQ1
Vss
/IRQ2
IRQ3
/RD
/WR
/CE
/ASTB
TESTSIO
RX0
TX0
RX1
TX1
Vss
Vdd
RX2
TX2/BO2
RX30
TX30
TX31
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
O
I
O
I
O
I
O
I
Data Bus
Interrupt Request Port 0
Interrupt Request Port 1
Ground
Interrupt Request Port 2
Interrupt Request Port 3
Read Signal Input
Write Signal Input
Chip Enable Input
Address Strobe (Not used: to ground)
Input with Pull-down Resistor (50 k)
Receive Data 0
Transmit Data 0
Receive Data 1
Transmit Data 1
Ground
Power Supply
Receive Data 2
Transmit Data 2
Receive Data 30
Transmit Data 30
Receive Data 31
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 TX31
RX32
TX32
RX33
TX33
/IC
Vss
XI
Vss
XO
A0
A1
A2
A3
A4
A5
CPUCLK
Vss
Vdd
D0
D1
D2
D3
D4
O
I
O
I
I/O
I
I
I/O
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
Transmit Data 31
Receive Data 32
Transmit Data 32
Receive Data 33
Transmit Data 33
Initial Clear
Ground
Quartz Crystal Input
Ground
Quartz Crystal Onput
Address Bus
CPU Clock
Ground
Power Supply
Data Bus
MBCG46183-129 (XV833A00) Gate Array
MAINCPU: IC128, 129
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DAUX
HDLT
DOUT
VFL
OPT
SYNC
MCC
WC
MCB
MCA
SKSY
XI
XO
P256
LOCK
Vss
TC
DIM1
DIM0
DOM1
DOM0
KM1
I
O
O
O
O
O
O
O
O
O
I
I
O
O
O
O
I
I
I
I
I
Auxiliary input for audio data
Asynchronous buffer operation flag
Audio data output
Parity flag output
Fs x 1 Synchronous output signal for DAC
Fs x 1 Synchronous output signal for DSP
Fs x 64 Bit clock output
Fs x 1 Word clock output
Fs x 128 Bit clock output
Fs x 256 Bit clock output
Clock synchronization control input
Crystal oscillator connection or external
clock input
Crystal oscillator connection
VCO oscillating clock connection
PLL lock flag
Logic section power (GND)
PLL time constant switching output
Data input mode selection
Data input mode selection
Data output mode selection
Data output mode selection
Clock mode switching input 1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
RSTN
Vdda
CTLN
PCO
(NC)
CTLP
Vssa
TSTN
KM2
KM0
FS1
FS0
CSM
EXTW
DDIN
LR
Vdd
ERR
EMP
CD0
CCK
CLD
I
I
O
I
I
I
I
O
O
I
I
I
O
O
O
O
I
I
System reset input
VCO section power (+5 V)
VCO control input N
PLL phase comparison output
VCO control input P
VCO section power (GND)
Test terminal. Open for normal use
Clock mode switching input 2
Clock mode switching input 0
Channel status sampling frequency
display output 1
Channel status sampling frequency
display output 0
Channel status output method selection
External synchronous auxiliary input
word clock
EIAJ (AES/EBU) data input
PLL word clock output
Logic section power (+5 V)
Data error flag output
Channel status emphasis control code
output
3-wire type microcomputer interface data
output
3-wire type microcomputer interface clock
input
3-wire type microcomputer interface load
input
YM3436DK (XG948E00) DIR2 (Digital Format Interface Receiver)
MAINCPU: IC141