
MCX-1000
A
1
2
3
4
5
6
7
8
9
B
C
D
E
F
G
H
I
J
K
L
68
SCHEMATIC DIAGRAM (MAIN: CPU Block)
★
All voltages are measured with a 10M
Ω
/V DC electronic voltmeter.
★
Components having special characteristics are marked
s
and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
Point 1 Pin 1 of IC107
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Auto-
power down
FORCEOFF
Vcc
GND
DOUT
FORCEON
DIN
INVALID
ROUT
EN
C1+
V+
C1-
C2+
C2-
V-
RIN
5k
Ω
IC101: MAX3221CPWR
RS-232C Line Driver/Receiver
IC102: PST572CMT-R
System Reset
+
Vcc
Out
Gnd
1
3
2
1
T/R
A0
A1
A2
A3
A4
A5
A6
A7
GND
VCC
OE
B0
B1
B2
B3
B4
B5
B6
B7
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
IC103: 74LCX245MTCX
IC104: 74VHCT245AMTCX
Low Voltage Bidirectional Transceiver
COLUMN DECODER
CELL ARRAY
BANK #0
ROW DECODER
SENSE AMPLIFIER
COLUMN DECODER
CELL ARRAY
BANK #1
ROW DECODER
SENSE AMPLIFIER
COLUMN DECODER
CELL ARRAY
BANK #2
ROW DECODER
SENSE AMPLIFIER
COLUMN DECODER
CELL ARRAY
BANK #3
ROW DECODER
SENSE AMPLIFIER
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
DATA CONTROL
CIRCUIT
DQ
BUFFER
MODE
REGISTER
CONTROL
SIGNAL
GENERATOR
DMn
DQ0
DQ15
UDQM
LDQM
CLK
CKE
CS
RAS
CAS
WE
A10
A0
A9
A11
BS0
BS1
IC105, 106: W986416DH-7
SDRAM
IC107: SN74AHC2GU04HDCTR
Triple Inverters
1A
3Y
GND
VCC
1Y
1
2
3
4
5
2A
3A
2Y
6
7
8
IC108: MBM29LV320BE90T
4Mbit Flash Memory
RY/BY
Buffer
State
Control
Command
Register
Erase Voltage
Generator
Input/Output
Buffers
Chip Enable
Output Enable
Logic
Address
Latch
X-Decoder
Y-Decoder
Y-Gating
Cell Matrix
Timer for
Program/Erase
Program Voltage
Generator
Low Vcc Detector
VCC
RY/BY
VSS
WE
CE
OE
STB
STB
DQ15 to DQ0
BYTE
A-1
A20 to A0
RESET
WP/ACC
Data Latch
IC110: 74LCX14MTCX
Low Voltage Hex Inverter
I0
O0
O1
VCC
I5
1
2
3
4
11
I1
O5
I4
12
13
14
I2
O2
O4
I3
5
6
7
O3
8
9
10
GND
1
47
48
2
1DIR
1A1
1B1
1OE
To Seven Other Channel
24
36
25
13
2DIR
2A1
2B1
2OE
To Seven Other Channel
IC113~120: SN74LVCHR16245AGR
16-bit Bus Transceiver
IC121: XC9572XL-10TQ100C
CPLD
I/O
Function
Block 1
Macrocells
1 to 18
I/O
Blocks
JTAG
Controller
In-System Programming Controller
F
a
st CONNECT II Switch Matr
ix
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O/GCK
I/O/GSR
I/O/GTS
2
54
18
1
JTAG Port
1
3
3
Function
Block 1
Macrocells
1 to 18
54
18
Function
Block 1
Macrocells
1 to 18
54
18
Function
Block 1
Macrocells
1 to 18
54
18
IC
1
VIN
GND
DC output
VCC
3
2
5
IC122: PQ018EZ01ZP
Regulator
3.3
3.3
3.3
3.3
3.3
5.0
5.0
5.0
0
0
5.0
5.0
0.1
3.3
3.3
3.3
3.3
0
0
0
0
0
0
0
0
3.3
0
0
3.3
0
3.7
1.8
3.3
2.7
0
0
1.8
1
0
0
0
3.3
0.1
3.3
0
5.0
0
3.3
0.1
3.3
0.1
1.9
5.0
0.1
3.3
0
3.3
0
0
3.3
0
3.2
3.3
0
0
3.3
MAIN CPU
RS232C DRIVER
VOLTAGE REGULATOR
SDRAM
FLASH ROM
BUS BUFFER
BUS BUFFER
CPLD
IC109
1
2
3
4
5
6
7
14
13
12
11
10
9
8
IC110
1
2
3
4
5
6
7
14
13
12
11
10
9
8