
MCX-1000
34
MCX-1000
207
PTL7(I)(Port)
AN7(I)(ADC)
DA0(O)(DAC)
F̲CONF̲DONE
I
FPGA config CONF̲DONE
206
PTL6(I)(Port)
AN6(I)(ADC)
DA1(O)(DAC)
NTSC̲N̲PAL
I
−
N
TSC/PAL select signal (LOW: PAL HIGH: NTSC)
204
PTL5(I)(Port)
AN5(I)(ADC)
DBG̲DIP1
I
−
D
ebugg board connector (R
everse Boot)
203
PTL4(I)(Port)
AN4(I)(ADC)
DBG̲DIP0
I
−
D
ebugg board connector
202
PTL3(I)(Port)
AN3(I)(ADC)
I
PS̲N̲STANDBY
201
PTL2(I)(Port)
AN2(I)(ADC)
I
−
A
GND
200
PTL1(I)(Port)
AN1(I)(ADC)
I
−
A
GND
199
PTL0(I)(Port)
AN0(I)(ADC)
I
−
A
GND
176
SCPT7(I)(Port)
IRQ5(I)(INTC)
/CTS2(I)(UART ch3)
IRQ5(I)(INTC)
ACDR̲N̲INT
I
(Pull-up OFF)
Interrupts signal from ACDR3
170
SCPT6(I/O)(Port)
/RTS2(O)(UART ch3)
TP
O
−
T
P
169
SCPT5(I/O)(Port)
SCK2(I/O)(UART ch3)
F̲DCLK
O
FPGA config DCLK
174
SCPT4(I)(Port)
RxD2(I)(UART ch3)
HOST̲RXD2
I
(RxD2)
−
AV AMP control RS232C RXD
168
SCPT4(O)(Port)
TxD2(O)(UART ch3)
HOST̲TXD2
O
(TxD2)
−
AV AMP control RS232C TXD
167
SCPT3(I/O)(Port)
SCK1(I/O)(UART ch2)
F̲N̲CONFIG
O
FPGA config nCONFIG
172
SCPT2(I)(Port)
RxD1(I)(UART ch2)
DBG̲RXD1
I
(RxD1)
−
Debugg board connector
166
SCPT2(O)(Port)
TxD1(O)(UART ch2)
DBG̲TXD1
O
(TxD1)
−
Debugg board connector
165
SCPT1(I/O)(Port)
SCK0(I/O)(UART ch1)
SH̲SCK0
O
(SCK0)
−
Synchronized serial clock
171
SCPT0(I)(Port)
RxD0(I)(UART ch1)
SH̲RxD0
I
(RxD0)
−
Synchronized serial RXD
164
SCPT0(O)(Port)
TxD0(O)(UART ch1)
SH̲TxD0
O
(TxD0)
−
Synchronized serial TXD
Note: When SCPT0, 2, 4 is used as a port, it can be assigned on
ly to either the input port or the output port.
SCPT
L
PLCR
0xFF00
SCPCR
0x1440
Port
Pin No.
Port Function
Other Function
Signal Name
I/O
Logic
Function
Register
Value
Positive
Negative
Negative
Negative
Negative
IC111 : HD6417709SF133 (MAIN P.C.B.)
µ
-COM (CPU)