Yamaha HTR-8063, Руководство по обслуживанию

Страница: 89 / 185

IC931: MB87L8760 (DIGITAL P.C.B.)
NPGA
*
No replacement part available. / サービス部品供給なし
Pin
No.
Port Name
Use
Port
Function
Name
Terminal
Processing
Related Power Supply
Detail of Function OFF ON
I/O Logic I/O Logic
32 SCK0 SPI0 SCK0 DSP_CLK DSP_PON O Low O Clk DSP comm u nication clock
33 SO0 SPI0 SO0 DSP_MOSI DSP_PON O Low O Data DSP transmission data
34 SI0 SPI0 SI0 DSP_MISO 10kPD DSP_PON I --- I Data DSP receive data
40 SCK1 SPI1 Usable as o u tp u t port
41 SO1 SPI1 Usable as o u tp u t port
42 SI1 SPI1
43 SCK2 SPI2 Usable as o u tp u t port
44 SO2 SPI2 Usable as o u tp u t port
47 SI2 SPI2
48 TXD0 UART0 TXD0 SR_MOSI
"5V lever shift
Raise $LCR SB"
SR_PON O Low O Data SIRIUS transmission data
49 RXD0 UART0 RXD0 SR_MISO
"3.3V level shift
10kPD"
SR_PON I --- I Data SIRIUS receive data
57 TXD1 UART1 TXD1 SCR_MOSI
"Switch to SCL2
with JW
Raise $LCR SB"
HDMI_PON O Low O Data Video scaler deb u g transmission data
58 RXD1 UART1 RXD1 SCR_MISO
"Switch to SDA2
with JW
10kPD"
HDMI_PON I --- I Data Video scaler deb u g receive data
69 TXD2 UART2 TXD2 IRB_MOSI Raise $LCR SB PRY O Low O Data IR blaster transmission data
70 RXD2 UART2 RXD2 IRB_MISO 10kPD PRY I --- I Data IR blaster receive data
11 SCL0 I2C0 SCL0 HEQ_SCL 2.2kPU HDMI_PON O Low O Clock HDMI switcher 100k I2C clock
12 SDA0 I2C0 SDA0 HEQ_SDA 2.2kPU HDMI_PON O Low I/O Data HDMI switcher 100k I2C data
25 SCL1 I2C1 SCL1 SCR_SCL 2.2kPU HDMI_PON O Low O Clock Video scaler 400k I2C clock
26 SDA1 I2C1 SDA1 SCR_SDA 2.2kPU HDMI_PON O Low I/O Data Video scaler 400k I2C data
27 SCL2 I2C2 SCL2
SCR_DBG_
SCL
"Switch to TXD1
with JW
2.2kPU"
HDMI_PON O Low O Clock Video scaler deb u g 400k I2C clock
28 SDA2 I2C2 SDA2
SCR_DBG_
SDA
"Switch to RXD1
with JW
2.2kPU"
HDMI_PON O Low I/O Data Video scaler deb u g 400k I2C data
109 PI0_MCLKI 0 IN RDS_RDY 10kPU+100kPD PRY I --- I H act RDS ready
111 PI1_LRCK 1 IN RDS_MISO 10kPD PRY I --- I Data RDS data
77 PI2_X0IN 2 IN GND at 0J if not assigned
80 PI3_X1IN 3 IN GND at 0J if not assigned
50 PI4_XCTS0 4 IN GND at 0J if not assigned
59 PI5_XCTS1 5 IN GND at 0J if not assigned
71 PI6_XCTS2 6 IN GND at 0J if not assigned
99 PO0_MCLKO 7 OUT RDS_CLK PRY O Low O Clock RDS clock
94 PO1_XLOCK 8 OUT RDS_RST PRY O Low O H act RDS reset
97 PO2 OUT
DAC_N_
RST_F
DSP_PON O Low O L act MainZone DAC reset Front (PCM1789)
98 PO3 OUT
DAC_N_
RST
DSP_PON O Low O L act
MainZone DAC reset Center/S u rro u nd/S u rro u nd
Back/SW (PCM1789)
51 PO4_XRTS0 OUT O Low O Low
60 PO5_XRTS1 OUT O Low O Low
72 PO6_XRTS2 13 OUT Open if not assigned
8 PWM0 14 OUT Open if not assigned
23 PWM1 15 OUT Open if not assigned
3 PIO0_0 [PIO0] 16 IN 10kPD HDMI_PON O Low O Low Set to OUT if not assigned
4 PIO0_1 [PIO1] 17 IN 10KPD HDMI_PON O Low O Low Set to OUT if not assigned
5 PIO0_2 [PIO2] 18 IN
HTX1_N_
INT
10kPU HDMI_PON I --- I L act HDMI TX1 interr u pt (reserve)
6 PIO0_3 [PIO3] 19 IN
HTX2_N_
INT
10kPU HDMI_PON I --- I L act HDMI TX2 interr u pt (reserve)
7 PIO0_4 [PIO4] 20 IN
DSP2_N_
SPIRDY
"4.7kPU at
100kPD and Net
31, 35"
DSP_PON O Low I L act DSP2 SPI ready
24 PIO0_5 [PIO5] 21 IN
SCR_N_
INT
10kPU HDMI_PON I --- I L act Interr u pt of scaler
31 PIO0_6 [PIO6] 22 IN 10kPD HDMI_PON O Low O Low Set to OUT if not assigned
35 PIO0_7 [PIO7] 23 IN 10kPD HDMI_PON O Low O Low Set to OUT if not assigned
89
RX-V1
067/HTR-8063/
RX-A1
0
0
0
RX-V1067/HTR-8063/RX-A1000
DRAFT