Yamaha HTR-8063, Руководство по обслуживанию

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Pin
No.
Port Name
F u nction
Name
Terminal
Processing
Processing
Condition
when not u sed
Condition when
u sed
Related Power S u pply
OFF Detail of F u nction
Condi-
tion
Proce-
ssing
DIR Logic I/O Logic
V1 BGPIO[7]
DSP2_N_
SPIRDY
4.7kPU – – I – No u sed (DSP2 SPI ready signal)
V2 BGPIO[8] DA_MUTE 10kPU – – O H act Zone DAC m u te
V3 BGPIO[9] – 10kPD Always I O Data
W1 SPI_SDI DSP_MISO 10kPD – – I SPI RX No u sed (DSP2 SPI MISO)
W2 SPI_SDO
NCPU_
PIC_MOSI
– – O SPI TX Image data
N25 BGPIO[16] BGPIO16 10kPD Always I – – Empty
N24 BGPIO[17] BGPIO17 10kPD Always I – – Empty
N23 BGPIO[18] BGPIO18 10kPD Always I – – Empty
P25 BGPIO[19] BGPIO19 10kPD Always I – – Empty
P24 BGPIO[20] BGPIO20 10kPD Always I – – Empty
P23 BGPIO[21] REV0
10kPU
GND at J
– – I Data
L: 2 types of crystals u sed H: 1 type of crystal u sed
Model distinction
Y2 BGPIO[2] 10kPD Always I – – Empty
R25 BGPIO[22] REV1
10kPU
GND at J
– – I Data No u sed (For hardware version)
R24 BGPIO[23] REV2
10kPU
GND at J
– – I Data No u sed (For hardware version)
R1 SDO_ABCK NCPU_BCK – – O Clock DSP_PON O Low A u dio o u tp u t bit clock
U2 BGPIO[11] – Always O/L – – Empty
P1 SDO_AWCK
NCPU_
WCK
– – O Clock DSP_PON O Low A u dio o u tp u t word clock
U3 BGPIO[12] – Always O/L – – Empty
U1 SDO_MCK
NCPU_
MCK
– – O Clock DSP_PON O Low A u dio o u tp u t master clock
P2 SDO3 NCPU_SD3 – – O Data No u sed (A u dio o u tp u t data 3)
P3 SDO2 NCPU_SD2 – – O Data No u sed (A u dio o u tp u t data 2)
R2 SDO1 NCPU_SD1 – – O Data No u sed (A u dio o u tp u t data 1)
R3 SDO0 NCPU_SD0 – – O Data DSP_PON O Low A u dio o u tp u t data 0
N1 SDI_ABCK GND – – I Clock No u sed
T2 BGPIO[14] DBG_DIP0 10kPU – – I Data DIP SW0 for deb u g
M1 SDI_AWCK GND – – I Clock No u sed
T3 BGPIO[15] DBG_DIP1 10kPU – – I Data DIP SW1 for deb u g
T1 SDI_MCK O/L – –
M2 SDI3 GND – – I Data No u sed
M3 SDI2 GND – – I Data No u sed
N2 SDI1 GND – – I Data No u sed
N3 SDI0 GND – – I Data No u sed
AE16 USBP USBP 15kPD – – B Data USB data +
AD16 USBM USBM 15kPD – – B Data USB data -
AB16 USB_PWEN
USB_
PWEN
– – O H act USB power enable
AC17 USB_OC USB_OC – – I H act USB over c u rrent detection
AE12
MAC_REF_
CLK
PHY01_
REF_CLK
– – O Clock MAC0 RMII clock o u tp u t
AE13 MAC0_RXD0
PHY0_
RXD0
– – I Data MAC0 RMII reception data 0
AD13 MAC0_RXD1
PHY0_
RXD1
– – I Data MAC0 RMII reception data 1
AC13 MAC0_RXER
PHY0_
RXER
4.7kPD – – I Data MAC0 RMII reception error
AE14 MAC0_TXD0
PHY0_
TXD0
– – O Data MAC0 RMII transmission data 0
AD14 MAC0_TXD1
PHY0_
TXD1
– – O Data MAC0 RMII transmission data 1
AC14 MAC0_TXEN
PHY0_
TXEN
– – O Data MAC0 RMII transmission enable
AD12
MAC0_CRS_
DV
PHY0_
CRS_DV
– – I Data MAC0 RMII career detection
AE15 MAC0_MDC PHY0_MDC – – O Clock MAC0 RMII MI clock
AD15 MAC0_MDIO
PHY0_
MDIO
4.7kPU – – B Data MAC0 RMII MI data
88
RX-V1
067/HTR-8063/
RX-A1
0
0
0
RX-V1067/HTR-8063/RX-A1000
DRAFT