Yamaha HTR-5065, Руководство по обслуживанию

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Pin No. Function Name I/O Detail of Function
Reset (active low). When asserted, the chip is placed in the reset state and the peripheral pins are
config
u red as inp u ts. After deassertion of NRESET, the chip is clocked by XTALI and starts booting from the
port config u red by the FCLE, FALE pins.
D13 NRESET I
The NRESET signal m u st be asserted after power- u p.
K3 XTALI I Oscillator circ u it inp u t. Internal system clock will be derived from XTALI (internal clock m u ltiplier).
J3 XTALO O Oscillator circ u it o u tp u t.
C7 RREF I Reference c u rrent. Connect a 3.0 k-ohms ±1% resistor to GND.
B10 TEST1 I Reserved. Connect to VDD for normal operation.
A10 HIGHZ I Reserved. Connect to VDD for normal operation.
E4
F4
G4
H4
J4
V1
n.c. – Pins m u st be left u nconnected (18x).
A4
A5
B4
B5
C8
C9
Pin No. Function Name I/O Detail of Function
J2
VCO[1:0] I
External oscillator inp u ts, typically coming from an external VCO. Together with the external loop-filter and
the internal clock dividers, each PDOUT/VCO pair can form a complete PLL.
K2
J1
PDOUT[1:0] O
Phase discriminator o u tp u ts. These signals are charge-p u mp type o u tp u ts.
K1 Each of them can be u sed to feed the loop-filter of a PLL str u ct u re.
Pin No. Function Name I/O Detail of Function
D12
C12
B12
A12
SSMD[7:0] I/O Data lines.
D11
C11
B11
A11
C10 SSMCLK O Clock o u tp u t.
A13 SSMCMD O Command o u tp u t.
D10 SSMCP I Card power inp u t (high = off).
D9 SSMWP I Write protect inp u t (low = protect).
SSM Interface
External PLL Pins
Global Pins
JTAG Interface
Pin No. Function Name I/O Detail of Function
B15 TMS I JTAG mode select.
C14 TCK I JTAG clock.
A16 TDI I JTAG serial data inp u t.
A15 TDO O JTAG serial data o u tp u t.
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RX-V573/HTR-5065
RX-V573/HTR-5065