Yamaha GX-505, Руководство по обслуживанию

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GX-505/GX-505VCD
GX-505/VCD
IC5 : MN35511AL [CD/VCD P.C.B.]
Signal Processor & Controller
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Function
Bit clock output for SR DATA
L/R identification signal output
Serial data output
Power supply for digital circuit
(+5)
GND for digital circuit
Digital audio interface output signal
Microprocessor command clock signal input (data latched at leading edge)
Microprocessor command data input
Microprocessor command load signal input
(L : LOAD)
Sense signal output (OFT, FESL, NACEND, NAJEND, SFG, NWTEND)
Focus servo drawing signal (L : when drawn)
Tracking servo drawing signal (L : when drawn)
Sub code block clock signal (BLKCK=75Hz)
Clock input for sub-code Q register
Sub-code Q code output
Muting input
(H : MUTE)
Status signal (CRC, STCNT, CLVS, TTSTOP, SQOK, RESY, FCLV, FLAG6, SENSE ,/FLOCK, /RFDET, /TLOCK)
Reset input
(L : RESET)
4.2336MHz clock signal output SMCK when command is defaulted. (Note 1) (NC)
SMCK (8.4672MHz), FCLK (7.35kHz) or “L” fixed is selected when command is switched.
With command defaulted : CLVS when IOSEL=H, FLAG6 when IOSEL=L
(NC)
These settings can be reversed by command (FLAG6 when IOSEL=H).
Traverse (Feed) forced feed output
3-State
Traverse (Feed) drive output
Spindle motor ON signal
L : ON (default) (NC)
Spindle motor drive signal (forced mode output) 3-State
Spindle motor drive signal (servo error signal output)
Kick pulse output
3-State
Tracking drive output
Focus drive output
Reference voltage for DA output block (TVD, ECS, TRD, FOD, FBAL, TBAL)
Focus balance adjustment output
Tracking balance adjustment output
Focus error signal input (analog input)
I/O
O
O
O
I
I
O
I
I
I
O
O
O
O
I
O
I
O
I
O
O
O
O
O
O
O
O
O
O
I
O
O
I
Name
BCLK
LRCK
SRDATA
DVDD1
DVSS1
TX
MCLK
MDATA
MLD
SENSE
FLOCK
TLOCK
BLKCK
SQCK
SUBQ
DMUTE
STAT
RST
SMCK/
FCLK
CLVS/
FLAG6
TRV
TVD
PC
ECM
ECS
KICK
TRD
FOD
VREF
FBAL
TBAL
FE
(Note 1) At the SMCK/FCLK pin, output does not stop while /RST=L.
29
58 59 56 17
S
TAT
X1 X2 XSEL
TIMING
GENERATOR
PITCH CONTROL
VCO
MICRO COMPUTER
INTERFACE
SERVO
CPU
OUTPUT
PORT
D/A
CONVERTER
EFM DEMODULATION
SYNC INTERPOLATION
SUBCODE DEMODULATION
CIRC ERROR CORRECTION
DEINTERLEAVE
CLV
SERVO
DIGITAL
AUDIO
INTERFACE
INTER POLATION
SOFT MUTING
DIGITAL
ATTENUATION
PEAK DETECT
AUTO CUE
DSL • PLL VCO
16k
SRAM
PEM
(L)
PEM
(R)
DD type
DAC
PLL
VCO 2
8 TIMES
OVER SAMPLING
DIGITAL FILTER
DIGITAL DE-EMPHASIS
SUBCODE
BUFFER
INPUT POR
T
SER
V
O
TIMING GENERA
T
O
R
A/D CONVER
TER
19
SMCK/FCLK
49
VCOF
69
CK384
8
M
D
ATA
7
MCLK
9
MLD
44
ARF
46
DRF
45
IREF
47
DSLF
48
PLLF
52
EFM
53
PCK/RESY
67
A
VDD
62
A
VSS
15
SUBQ
14
SQCK
20
CL
VS/FLA
G6
68
DEMPO
73
SUBC
72
SBCK2
74
SBCK
75
CLDCK
13
BLKCK
55
CRC
78
SD
A
T
I
80
BCKI
79
LRCKI
77
DEMPI/TEST2
61 VCOF2
70
IOSEL
41
T
OFS
40 10 43
LDON
SENSE
WVEL
11
/FLOCK
12
/TLOCK
30
FBAL
31
TBAL
28
FOD
27
TRD
22
TVD
25
ECS
42
PLA
Y/TR
VSTP
29
VREF
21
TR
V
16
DMUTE
1
BCLK
3
SRD
A
T
A
2
LRCK
23
PC
24
ECM
6
TX
76
IPFLA
G
54
FLA
G
51
A
VSS2
63
OUT1C
65
OUT2D
38 /RFDET
39 BDO
35
VDET
37 TRCRS
34 RFENV
33 TE
32 FE
71 /TEST
18
/RST
5 DVSS1
4 DVDD1
57
VSS
60 VDD
36 OFT
50
A
VDD2
64
OUT1D
66
OUT2C
26
KICK