CLP-955
20
PIN
No.
NAME
I/O
FUNCTION
PIN
No.
NAME
I/O
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LRCK
DATA
BCK
CLKO
XTI
XTO
DGND
VDD
Vcc2R
AGND2R
ENTR
NC
VOUTR
AGND1
I
I
I
O
I
O
-
-
-
-
O
-
O
-
Data input
Bit clock
Clock input
Clock input
clock out
Digital ground
Digital power supply (+5V)
Analog power supply (+5V)
Analog ground
Rch, analog output
Rch, analog voltage outpput
Analog ground
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Vcc1
VOUTL
NC
EXTL
AGND2L
Vcc2L
/ZERO
/RST
/CS/IWO
MODE
/MUTE
MD/DM0
MC/DM1
ML/IIS
-
O
-
O
-
-
O
I
I
I
I
I
I
I
Analog power supply (+5V)
Lch, analog voltage output
Lch, analog output
Analog ground
Analog power supply (+5V)
Zero data flag
Reset
Chip select
Mode control select
(h: Software, L: hardware)
mute control
mode control data/De-emphasis select1
mode control BCK/De-emphasis select2
mode control Latch/input format select
PCM1716E (XU829A00) DAC (Digital to Analog Converter)
DM: IC610
PIN
No.
NAME
I/O
FUNCTION
PIN
No.
NAME
I/O
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
BK5
BK4
BK3
BK2
BK1
BK0
MK15
MK14
MK13
MK12
MK11
MK10
MK05
MK04
MK03
MK02
MK01
MK00
XIN
XOUT
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
O
Key block (open drein)
First make contact
Second make contact
Crystal osc. input (4 MHz)
Crystal osc. output (4 MHz)
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
VDD
SO
ACK
XCK
/IC
TST1
TST2
XCKINH
BK14
BK13
BK12
BK11
BK10
BK9
BK8
BK7
BK6
GND
VDD
O
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
Ground
Power supply
Serial data
Acknowledge/mode select
Clock for serial data
Initial clear
Test mode
(L,L: normal mode, others: test)
Inhibit of serial clock
Key block (open drein)
Ground
Power supply
YMZ702-D (XR632A00) KSN2 (Key Scanner)
AEXL88-L: KSN2
