xTAG v3.0 Hardware Manual
4/8
5V
MSEL
TDSCR
TMS
TCK
DEBUG
TDSNK
RST_N
UART_RX
UART_TX
1
2
19 20
NC
GND
XL1_UP1
GND
XL1-_UP0
GND
XL1-DN0
GND
XL1-DN1
GND
Figure 2:
xTAG v3.0
xSYS pinout
Pin
xCONNECT Link
X0D52
XL1_UP1
X0D53
XL1_UP0
X0D54
XL1_DN0
X0D55
XL1_DN1
3.2
JTAG Configuration
Some of the I/O pins on the microcontroller are driven by the JTAG signals. The
mapping of the signals to the pins is shown in the table below:
Pin
Port
Processor
X0D11
P1D0
TDSRC
X0D13
P1F0
TDSNK
X0D22
P1G0
TMS
X0D10
P1C0
TCK
X0D70
P32A19
MSEL
XM006125A
