XMOS xTAG v3.0, Руководство по оборудованию

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xTAG v3.0 Hardware Manual 3/8
Pin Signal Direction Description
1 5V Target to Host Power
2 NC N/A No connection
3 MSEL Host to Target Select boot from JTAG - Active Low
4 GND N/A Ground
5 TDSRC Host to Target JTAG Test Data
6 XL1_UP1 Target to Host xCONNECT Link
7 TMS Host to Target JTAG Test Mode Select
8 GND N/A Ground
9 TCK Host to Target JTAG Test Clock
10 XL1_UP0 Target to Host xCONNECT Link
11 DEBUG Bidirectional Debug
12 GND N/A Ground
13 TDSNK Target to Host JTAG Test Data
14 XL1_DN0 Host to Target xCONNECT Link
15 RST_N Host to Target System Reset - Active Low
16 GND N/A Ground
17 UART_RX Host to Target Serial Port
18 XL1_DN1 Host to Target xCONNECT Link
19 UART_TX Target to Host Serial Port
20 GND N/A Ground
The routing of these I/O pins along with the power pins is shown below.
3.1 xCONNECT Link configuration
Some of the I/O pins on the processor are configured as a duplex 2-bit serial
xCONNECT Link. The mapping of xCONNECT Link to the pins is shown in the table
below:
XM006125A