Xilinx Zynq UltraScale+, Руководство пользователя

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Zynq Ult VCU TRD User Guide 77
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 5: Hardware Platform
Table 5-8 shows interrupt ID mapping for an Ethernet 10G design.
Table 5-9 shows interrupt ID mapping for an SDI design.
Audio Formatter MM2S 2 106
Audio Formatter S2MM 2 107
I2S transmitter 108
I2S receiver 109
Interrupt Controller 110
Table 5-8: Interrupt ID Map for Ethernet 10G Design
IP Core Interrupt ID
HDMI I2C Controller 94
HDMI 1.4/2.0 Transmitter Subsystem v2.0 93
Video Mixer 95
HDMI Frame Buffer Read 89
HDMI Frame Buffer Write 0 90
HDMI 1.4/2.0 Receiver Subsystem v2.0 91
Video PHY Controller 92
VCU 96
DMA S2MM 104
DMA MM2S 105
HDMI Frame Buffer Write 1 106
HDMI Frame Buffer Write 2 107
Table 5-9: Interrupt ID Map for SDI Design
IP Core Interrupt ID
Audio Formatter mm2s 96
Audio Formatter s2mm 97
Frame Buffer Read 91
Frame Buffer Read 104
Frame Buffer Write 92
Frame Buffer Write 105
SDI Audio Extract 93
SDI RX 89
SDI TX 90
Table 5-7: Interrupt ID Map for VCU Audio Design (Cont’d)
IP Core Interrupt ID
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