manualshive.com logo in svg

Xilinx Virtex-5 LXT, Руководство пользователя

Поделиться
Скачать
Xilinx Virtex-5 LXT Скачать руководство пользователя страница 25

Virtex-5 LXT/SXT/FXT FPGA Prototype Platform

www.xilinx.com

25

UG229 (v3.0.1) May 21, 2008

Detailed Description

R

20. SPI Interface

The SPI interface is a four-wire, synchronous serial data bus configuration. The interface 
utilizes a 64-Mb STMicroelectronics low-voltage, serial Flash memory device (U10), part 
number M25P64, which can be used for FPGA configuration or to hold user data. A SPI 
system typically consists of a master device and at least one slave device. For Virtex-5 
FPGA configuration, the FPGA is the SPI master and the SPI Flash PROM is the slave 
device. The SPI interface uses four signals (

Table 12

) to communicate between the FPGA 

and the Flash PROM device.

The J2 connector allows users to connect a Parallel Cable IV ribbon cable to configure the 
SPI device. For SPI programming, refer to the latest version of Xilinx iMPACT software tool 
documentation 

[Ref 6]

. To set the Mode pins for SPI configuration, see the 

Virtex-5 FPGA 

Configuration User Guide

 

[Ref 3]

. The PROGRAM pin must be held Low when configuring 

the SPI device. After configuring the SPI device, the PROGRAM pin must be released to 
configure the FPGA from the SPI device.

Table 12:

SPI Pins

Label

 Pin Number For Package Type

FF665

FF1136

FF1738

Serial Clock (C)

J11

 N15

AH14

Serial Data Out (Q)

J10 

 P15

R15

Chip Select (S_N)

Y12 

 AE14

AL14

Serial Data In (D)

AA12

 AF14

AM13

Содержание Virtex-5 LXT

Страница 1: ...R P N 0402534 03 Virtex 5 LXT SXT FXT FPGA Prototype User Guide optional UG229 v3 0 1 May 21 2008 optional Virtex 5 LXT SXT FXT FPGA Prototype Platform User Guide UG229 v3 0 1 May 21 2008...

Страница 2: ...ORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUE...

Страница 3: ...ion 13 1 Power Switch 13 2 Power Supply Jacks 15 3 Configuration Ports 16 4 JTAG Chain 17 5 JTAG Termination Header 17 6 Upstream Downstream Connectors 18 7 Prototyping Area 20 8 VCCO Enable Supply Ju...

Страница 4: ...4 www xilinx com Virtex 5 LXT SXT FXT FPGA Prototype Platform UG229 v3 0 1 May 21 2008 R...

Страница 5: ...The features and product selection of the Virtex 5 family are outlined in this overview Virtex 5 FPGA Data Sheet DC and Switching Characteristics This data sheet contains the DC and Switching Characte...

Страница 6: ...or User Guide The System Monitor functionality available in all the Virtex 5 devices is outlined in this guide Virtex 5 FPGA Packaging and Pinout Specifications This specification includes the tables...

Страница 7: ...Example Blue text Cross reference link to a location in the current document See the section Additional Support Resources for details Refer to Clock Management Technology in Chapter 2 for details Red...

Страница 8: ...8 www xilinx com Virtex 5 LXT SXT FXT FPGA Prototype Platform UG229 v3 0 1 May 21 2008 Preface About This Guide R...

Страница 9: ...ctionality of Virtex 5 FPGA features and are not intended for A C characterization or high speed I O evaluation Features Independent power supply jacks for VCCINT VCCO and VCCAUX Selectable VCCO enabl...

Страница 10: ...nfiguration solution or by chaining another board The downstream connectors can be used to connect to another board in a chain for serial configuration A maximum of two boards can be chained together...

Страница 11: ...ration Upstream Interface Connector Downstream Interface Connector Downstream System ACE Interface Connector LVTTL 2x 2x Diff Pair Clocks SMA SMA Power Bus and Switches 5V Jack 5V Brick or VCC Jack VC...

Страница 12: ...136 or FF1738 prototype platform users should be familiar with Xilinx resources See References for direct links to Xilinx documentation See the following locations for additional documentation on Xili...

Страница 13: ...jack J32 On Position In the ON position the power switch enables delivery of all power to the board by way of voltage regulators situated on the backside of the board These regulators feed off a 5V ex...

Страница 14: ...evices 1 2V for LXT and SXT devices Table 2 Power Enable Jumpers Header Description J19 J20 J21 These headers are in each power supply and are marked REG ENABLE Placement of jumpers on these headers e...

Страница 15: ...proper operation 2 Power Supply Jacks One method of delivering power to the DUT is by way of the power supply jacks VCCINT J33 VCCO J31 and VCCAUX J30 See Virtex 5 FPGA Data Sheet DC and Switching Ch...

Страница 16: ...mode connectivity between the configuration port header and a Parallel Cable III or Parallel Cable IV flying wire cable PC4 JTAG Configuration Interface The JTAG configuration port J1 for the board a...

Страница 17: ...the JTAG termination header J22 otherwise jumper pins 2 3 for on board termination The TCK and TMS pins are parallel feedthrough connections from the upstream System ACE interface connector to the do...

Страница 18: ...rface connector P3 is used to pass configuration information to a DUT in a downstream prototype platform board from sources such as a Parallel Cable III cable or an upstream System ACE interface conne...

Страница 19: ...downstream interface connector of another prototype platform board X Ref Target Figure 7 Figure 7 Upstream Interface Connector 44 Pin Female UG229_07_051506 RW_B D6 D7 DONE CCLK DOUT_BUSY D1 D2 DIN D3...

Страница 20: ...VCCO_34 each with a VCCO enable supply jumper The VCCO enable supply jumpers can connect each bank to one of the two onboard supplies the VCCINT or VCCO supplies These jumpers must be installed for th...

Страница 21: ...on to an external function generator These connect to the DUT clock pads Table 7 They can also be used as differential clock inputs The differential clock pairings differential pairs are as shown in T...

Страница 22: ...red to the breakout area to use with certain types of oscilloscope probes for either connecting function generators or wiring pins to the pin breakout area Table 8 shows the clocks in the pin breakout...

Страница 23: ...configuration the LEDs are available to the user and reflect the status of pins D0 D7 and D24 D31 corresponding to LED 0 LED 15 Table 9 shows the LED assignments Table 9 LED Assignments and Correspon...

Страница 24: ...fully powered up and completed its internal power on process 19 Platform Flash ISPROM A 32 Mb Platform Flash ISPROM U4 is provided on the board for configuration Table 11 Refer to the Platform Flash I...

Страница 25: ...e SPI interface uses four signals Table 12 to communicate between the FPGA and the Flash PROM device The J2 connector allows users to connect a Parallel Cable IV ribbon cable to configure the SPI devi...

Страница 26: ...BPI Pins Label Pin Number For Package Type FF665 FF1136 FF1738 DQ0 AA15 AD19 AJ26 DQ1 Y15 AE19 AK27 DQ2 W14 AE17 AM14 DQ3 Y13 AF16 AN14 DQ4 W16 AD20 AK29 DQ5 Y16 AE21 AK28 DQ6 AA14 AE16 AP13 DQ7 AA13...

Страница 27: ...dress 23 and address 24 to FPGA IOBs Jumper pins 3 to 5 and pins 4 to 6 connect RS0 and RS1 to the highest address lines of the BPI device See the Virtex 5 FPGA Configuration User Guide Ref 3 for more...

Страница 28: ...e GTP GTX transceivers are looped back and are not connected to test points or SMA connectors See the Virtex 5 FPGA RocketIO GTP Transceiver User Guide Ref 4 and the Virtex 5 FPGA RocketIO GTX Transce...

Страница 29: ...or each mode pin sets logic 0 removing the jumper sets logic 1 The default value 000 corresponds to the Master Serial configuration mode Table 15 Configuration Mode Pin Jumper Settings Configuration M...

Страница 30: ...irtex 5 devices 1 DS100 Virtex 5 Family Overview 2 DS202 Virtex 5 FPGA Data Sheet DC and Switching Characteristics 3 UG190 Virtex 5 FPGA User Guide 4 UG196 Virtex 5 FPGA RocketIO GTP Transceiver User...

Отзывы:

Нет отзывов

Бренды по названию

Популярные бренды

Загрузить еще бренды