Xilinx Virtex-5 LXT, Руководство пользователя

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22 www.xilinx.com Virtex-5 LXT/SXT/FXT FPGA Prototype Platform
UG229 (v3.0.1) May 21, 2008
Detailed Description
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12. DUT Socket
The DUT socket (U1) contains the user FPGA. The DUT must be oriented using the P1
indicator on the board.
Caution!
Failure to insert the device to the proper orientation can damage the device. To avoid
pin damage, always use the vacuum tool provided when inserting or removing the Virtex-5
device. When using BGA packages, do not apply pressure to the device while activating the
socket. Doing so can damage the socket and/or the device.
13. Pin Breakout
The pin breakout area is used to monitor or apply signals to each of the DUT pins. Headers
can be soldered to the breakout area to use with certain types of oscilloscope probes, for
either connecting function generators or wiring pins to the pin breakout area.
Table 8
shows the clocks in the pin breakout area that connect to the DUT clock pads.
Table 8: Breakout Clock Pin Connections
Label Clock Name
Pin Number
FF665 FF1136 FF1738
Break
out Area
IO_L2P_GC_VRN_3 D14 G15 J17
IO_L2N_GC_VRP_3 D13 G16 K17
IO_L3P_GC_3 E17 K18 M27
IO_L3N_GC_3 D18 J19 M28
IO_L4P_GC_3 E13 J16 L17
IO_L4N_GC_VREF_3 E12 J17 M17
IO_L5P_GC_3 E18 L19 L29
IO_L5N_GC_3 F19 K19 K28
IO_L6P_GC_3 F12 H14 L16
IO _L6N _GC_3 E11 H15 L15
IO_L7P_GC_3 E20 J20 K29
IO _L7N _GC _3 E21 J21 J30
IO_L8P_GC_3 E10 J14 L14
IO_L8N_GC_3 F10 H13 K15
IO_L4P_GC_4 AB19 AG21 AP27
IO_L4N_GC_VREF_4 AC19 AG20 AN28
IO_L5P_GC_4 AC12 AH15 AM16
IO_L5N_GC_4 AC13 AG15 AM17
IO_L7P_GC_VRN_4 AB14 AH17 AN15
IO_L7N_GC_VRP_4 AC14 AG16 AN16